DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 106

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 3 to 0: T4 APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0 = 0, the T4 APLL DFS is connected to
the T4 DPLL, and this field configures the T4 APLL DFS frequency. The T4 APLL DFS frequency affects the
frequency of the T4 APLL which in turn affects the available output frequencies on the output clock pins (see the
OCR
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
registers). See Section 7.8.2.
T4FREQ[3:0]
1101–1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
—
7
0
T4 APLL DFS FREQUENCY
25.248MHz (4 x 6312kHz)
40.000MHz (4 x 10MHz)
26.000MHz (2 x 13MHz)
62.500MHz (GbE  16)
37.056MHz (24 x DS1)
24.704MHz (16 x DS1)
30.720MHz (3 x 10.24)
APLL output disabled
24.576MHz (12 x E1)
32.768MHz (16 x E1)
68.736MHz (2 x E3)
—
6
0
44.736MHz (DS3)
{unused values}
T4CR1
T4 DPLL Configuration Register 1
64h
77.76MHz
—
5
0
—
4
0
T4 APLL FREQUENCY (4 x T4 APLL DFS)
100.992MHz (16 x 6312kHz)
311.04MHz (4 x 77.76MHz)
160.000MHz (16 x 10MHz)
104.000MHz (8 x 13MHz)
122.880MHz (12 x 10.24)
148.224MHz (96 x DS1)
250.000MHz (GbE  4)
98.816MHz (64 x DS1)
178.944MHz (4 x DS3)
0
Disabled, output is low
3
131.072MHz (64 x E1)
98.304MHz (48 x E1)
274.944MHz (8 x E3)
{unused values}
2
1
T4FREQ[3:0]
0
1
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1
0