DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 111

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 6 to 4: Phase Detector 2 Gain, 8kHz (PD2G8K[2:0]). This field specifies the gain of the T0 phase detector 2
with an input clock of 8kHz or less. This value is only used if automatic gain selection is enabled by setting PD2EN
= 1 in the
Bits 2 to 0: Damping Factor (DAMP[2:0]). This field configures the damping factor of the T0 DPLL. Damping
factor is a function of both DAMP[2:0] and the T0 DPLL bandwidth
corresponds to a damping factor of 5. See Section 7.7.4.
The gain peak for each damping factor is shown below:
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
000, 110, and 111 =
DAMPING
FACTOR
001 =
010 =
011 =
100 =
101 =
1.2
2.5
10
20
T0CR3
5
—
7
0
register. See Section 7.7.5.
GAIN PEAK (dB)
 4Hz
5
5
5
5
5
6
0
0.06
0.03
0.4
0.2
0.1
T0CR2
T0 Configuration Register 2
6Bh
PD2G8K[2:0]
8Hz
2.5
5
5
5
5
5
0
{unused values}
18Hz
1.2
2.5
5
5
5
4
1
35Hz
1.2
2.5
10
10
5
—
0
3
(T0ABW
≥ 70Hz
1.2
2.5
10
20
5
and T0LBW). The default value
2
0
DAMP[2:0]
1
1
111 of 142
0
1