DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 84

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Automatic Bandwidth Selection (AUTOBW). See Section 7.7.3.
Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL’s integral path is limited (i.e., frozen)
when the DPLL reaches minimum or maximum frequency, as set by the HARDLIM field in
When the integral path is frozen, the current DPLL frequency in registers FREQ1,
frozen. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in. See Section 7.7.3.
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
0 = Always selects locked bandwidth from the
1 = Automatically selects either locked bandwidth
0 = Do not freeze integral path at min/max frequency.
1 = Freeze integral path at min/max frequency.
register) as appropriate.
AUTOBW
7
1
—
6
1
MCR9
Master Configuration Register 9
3Bh
—
5
1
T0LBW
—
4
1
(T0LBW
register.
LIMINT
register) or acquisition bandwidth
1
3
—
2
0
FREQ2
DLIMIT1
—
1
1
and
FREQ3
(T0ABW
and DLIMIT2.
84 of 142
—
0
1
is also