DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 133

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

10.2 Input Clock Timing
Table 10-7. Input Clock Timing
(V
10.3 Output Clock Timing
Table 10-8. Input Clock to Output Clock Delay
Table 10-9. Output Clock Phase Alignment, Frame-Sync Alignment Mode
See Section
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
Input Clock
Period
Input Clock High, Low Time
DD
FREQUENCY
8kHz (FSYNC)
FREQUENCY
155.52MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
44.736MHz
34.368MHz
155.52MHz
311.04MHz
= 1.8V 10%; V
6.48MHz
1.544MHz
2.048MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
OUTPUT
6.48MHz
INPUT
8kHz
2kHz
8kHz
7.9.2
PARAMETER
for details on frame-sync alignment and the SYNC[1:3] pins.
CMOS/TTL Input Pins
LVDS/LVPECL Input Pins
DDIO
FREQUENCY
155.52MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
MFSYNC FALLING EDGE TO OUTPUT
OUTPUT
6.48MHz
= 3.3V 5%, T
CLOCK FALLING EDGE DELAY (ns)
8kHz
-2.0  1.25
-2.0  1.25
-2.0  1.25
-2.0  1.25
-2.0  1.25
-2.0  1.25
-2.0  1.25
-2.0  1.25
-2.0  1.25
-2.0  1.25
0  1.25
0  1.25
A
0  0.5
0  0.5
0  0.5
INPUT CLOCK EDGE TO
OUTPUT CLOCK EDGE
= -40°C to +85°C.)
DELAY (ns)
SYMBOL
0  1.5
0  1.5
0  1.5
0  1.5
0  1.5
0  1.5
0  1.5
0  1.5
t
t
H
CYC
, t
L
whichever is smaller
6.4ns (156.25MHz)
3ns or 30% of t
8ns (125MHz)
MIN
CYC
,
TYP
500s (2kHz)
500s (2kHz)
133 of 142
MAX