DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 119

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The PHASE1 and PHASE2 registers must be read consecutively. See Section 8.3.
Bits 7 to 0: Current DPLL Phase (PHASE[7:0]). The full 16-bit PHASE[15:0] field spans this register and the
PHASE2
detector. The value is the output of the phase averager. When T4T0 = 0 in the
the current phase of the T0 DPLL. When T4T0 = 1, PHASE indicates the current phase of the T4 DPLL. The
averaged phase difference in degrees is equal to PHASE  0.707. See Section 7.7.10.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Current DPLL Phase (PHASE[15:8]). See the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 6: Phase-Lock Timeout Multiplier (PHLKTOM[1:0]). This field is an unsigned integer that specifies
the resolution of the phase-lock timeout field PHLKTO[5:0].
Bits 5 to 0: Phase-Lock Timeout (PHLKTO[5:0]). This field is an unsigned integer that, together with the
PHLKTOM[1:0] field, specifies the length of time that the T0 DPLL attempts to lock to an input clock before
declaring a phase-lock alarm (by setting the corresponding LOCK bit in the
seconds is PHLKTO[5:0]  2^(PHLKTOM[1:0] + 1). The state machine remains in the prelocked, prelocked 2, or
phase-lost modes for the specified time before declaring a phase alarm on the selected input. See Section 7.7.1.
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
00 = 2 seconds
01 = 4 seconds
10 = 8 seconds
11 = 16 seconds
register. PHASE is a two’s-complement signed integer that indicates the current value of the phase
7
0
7
0
PHLKTOM[1:0]
0
7
6
0
6
0
0
6
PHASE1
Phase Register 1
77h
PHASE2
Phase Register 2
78h
PHLKTO
Phase-Lock Timeout Register
79h
5
0
5
0
5
1
4
0
4
0
4
1
PHASE[15:8]
PHASE[7:0]
PHASE1
0
0
register description.
0
3
3
3
PHLKTO[5:0]
ISR
MCR11
2
0
2
0
2
0
registers). The timeout period in
register, PHASE indicates
1
0
1
1
1
0
119 of 142
0
0
0
0
0
0