DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 4

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

____________________________________________________________________________________________ DS3102
List of Figures
Figure 2-1. Typical Application Example ..................................................................................................................... 7
Figure 3-1. Block Diagram ........................................................................................................................................... 8
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 26
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 28
Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 31
Figure 7-4. FSYNC 8kHz Options.............................................................................................................................. 45
Figure 7-5. SPI Clock Phase Options ........................................................................................................................ 51
Figure 7-6. SPI Bus Transactions.............................................................................................................................. 52
Figure 9-1. JTAG Block Diagram............................................................................................................................. 124
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 126
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 131
Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins .............................................. 131
Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins .................................................... 132
Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 135
Figure 10-5. JTAG Timing Diagram......................................................................................................................... 136
Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 137
Figure 11-1. Pin Assignment Diagram..................................................................................................................... 139
19-4617; Rev 5; 8/10
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