DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 35

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

____________________________________________________________________________________________ DS3102
7.7.7.4 PBO Phase Offset Adjustment
An uncertainty of up to 5ns is introduced each time a phase build-out event occurs. This uncertainty results in a
phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The
PBOFF
register specifies a small fixed offset for each phase build-out event to skew the average error toward zero and
eliminate accumulation of phase shifts in one direction.
7.7.8 Input to Output (Manual) Phase Adjustment
When phase build-out is disabled (PBOEN = 0 in MCR10), the
OFFSET
registers can be used to adjust the phase
of the T0 DPLL output clocks with respect to the selected reference when locked. Output phase offset can be
adjusted over a 200ns range in 6ps increments. This phase adjustment occurs in the feedback clock so that the
output clocks are adjusted to compensate. The rate of change is therefore a function of DPLL bandwidth. Simply
writing to the
OFFSET
registers with phase build-out disabled causes a change in the input to output phase, which
can be considered to be a delay adjustment. Changing the OFFSET adjustment while in free-run or holdover state
does not cause an output phase offset until it exits the state and enters one of the locking states.
7.7.9 Phase Recalibration
When a phase buildout occurs, either automatic or manual, the feedback frequency synthesizer does not get an
internal alignment signal to keep it aligned with the output dividers, and, therefore, the phase difference between
input and output can become incorrect. Setting the FSCR3:RECAL bit periodically causes a recalibration process
to be executed, which corrects any phase error that may have occurred.
During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to
zero, resets all clock dividers, ramps the phase offset to the value stored in the
OFFSET
registers, and switches
the DPLL out of mini-holdover. If the
OFFSET
registers are written during the recalibration process, the process
ramps the phase offset to the new offset value.
7.7.10 Frequency and Phase Measurement
When the T4 DPLL is not needed to generate an output frequency locked to an input clock, it can measure precise
frequency by locking onto any input. It can also measure phase between the T0 selected reference and any input
by setting the T0CR1.T4MT0 bit. The T4 APLL can still be used to clean up jitter on a synthesized clock from the
T0 DPLL. When the T0CR1.T4MT0 bit is set the T4 DPLL goes to the free-run state.
Standard input clock frequency monitoring is described in Section 7.5.1. The input clock monitors report measured
frequency with 3.8ppm resolution. More accurate measurement of frequency and phase can be accomplished
using the DPLLs. The T0 DPLL is always monitoring its selected reference, but if the T4 DPLL is not otherwise
used to lock to an input, it can be configured as a high-resolution phase monitor. The REFCLK signal accuracy
after being adjusted with MCLKFREQ is used for the frequency reference. Software can then connect the T4 DPLL
to various input clocks on a rotating basis to measure phase between the T0 DPLL input and another input. See
the T4FORCE field of MCR4.
DPLL frequency measurements can be read from the FREQ field spanning registers FREQ1, FREQ2, and FREQ3.
This field indicates the frequency of the selected reference for either the T0 DPLL or the T4 DPLL, depending on
the setting of the T4T0 bit in MCR11. This frequency measurement has a resolution of 0.0003068ppm over a
80ppm range. The value read from the FREQ field is the DPLL’s integral path value, which is an averaged
measurement with an averaging time inversely proportional to DPLL bandwidth.
DPLL phase measurements can be read from the PHASE field spanning registers
PHASE1
and PHASE2. This
field indicates the phase difference seen by the phase detector for either the T0 DPLL or the T4 DPLL, depending
on the setting of the T4T0 bit in MCR11. This phase measurement has a resolution of approximately 0.703 degrees
and is internally averaged with a -3dB attenuation point of approximately 100Hz. Thus, for low DPLL bandwidths,
the PHASE field gives input phase wander in the frequency band from the DPLL corner frequency up to 100Hz.
This information could be used by software to compute a crude MTIE measurement.
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