DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 85

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field
spans this register and
204.8MHz master clock with respect to the frequency of the local oscillator clock on the REFCLK pin by up to
+514ppm and -771ppm. The master clock adjustment has the effect of speeding up the master clock with a positive
adjustment and slowing it down with a negative adjustment. For example, if the oscillator connected to REFCLK
has an offset of +1ppm, the adjustment should be -1ppm to correct the offset.
The formulas below translate adjustments to register values and vice versa. The default register value of 39,321
corresponds to 0ppm. See Section 7.3.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[15:8]). See the
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
MCLKFREQ[15:0] = adjustment_in_ppm / 0.0196229 + 39,321
adjustment_in_ppm = (MCLKFREQ[15:0] – 39,321)  0.0196229
7
1
7
1
MCLK2.
6
0
6
0
MCLK1
Master Clock Frequency Adjustment Register 1
3Ch
MCLK2
Master Clock Frequency Adjustment Register 2
3Dh
MCLKFREQ is an unsigned integer that adjusts the frequency of the internal
5
0
5
0
MLCKFREQ[15:8]
MCLKFREQ[7:0]
4
1
4
1
1
1
3
3
MCLK1
2
0
2
0
register description.
1
0
1
0
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0
1
0
1