DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 90

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DS3102GN

Manufacturer Part Number
DS3102GN
Description
Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
Manufacturer
Maxim Integrated Products
Datasheet

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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Interrupt Enable for Frame-Sync Input Monitor Alarm (FSMON). This bit is an interrupt enable for the
FSMON bit in the
Bit 6: Interrupt Enable for the T4 DPLL Lock Status Change (T4LOCK). This bit is an interrupt enable for the
T4LOCK bit in the
Bit 5: Interrupt Enable for Phase Monitor Alarm (PHMON). This bit is an interrupt enable for the PHMON bit in
the
Bit 4: Interrupt Enable for T4 No Valid Inputs Alarm (T4NOIN). This bit is an interrupt enable for the T4NOIN bit
in the
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
MSR3
MSR3
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
register.
register.
FSMON
MSR3
MSR3
7
0
register.
register.
T4LOCK
6
0
IER3
Interrupt Enable Register 3
45h
PHMON
5
0
T4NOIN
4
0
3
0
2
0
1
0
90 of 142
0
0

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