LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 132

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12 GPIO/LED Controller
Revision 1.4 (07-07-10)
12.1
12.2
12.2.1
The GPIO/LED Controller provides 6 configurable general purpose input/output pins, GPIO[5:0]. These
pins can be individually configured to function as inputs, push-pull outputs, or open drain outputs and
each is capable of interrupt generation with configurable polarity. Alternatively, all 6 GPIO pins can be
configured as LED outputs, enabling these pins to drive Ethernet status LEDs for external indication
of various attributes of the switch ports.
GPIO and LED functionality is configured via the GPIO/LED System Control and Status Registers
(CSRs). These registers are defined in
The GPIO controller is comprised of 6 programmable input/output pins. These pins are individually
configurable via the GPIO CSRs. On application of a chip-level reset:
Note: GPIO[5:0] may be configured as LED outputs by default, dependant on the
The direction and buffer type of all 6 GPIOs are configured via the
Register (GPIO_CFG)
direction of each GPIO, input or output, should be configured first via its respective
0 (GPDIR[5:0])
configured as an output, the output buffer type for each GPIO is selected by the
0 (GPIOBUF[5:0])
open-drain output buffers are supported for each GPIO. When functioning as an open-drain driver, the
GPIO output pin is driven low when the corresponding
Purpose I/O Data & Direction Register (GPIO_DATA_DIR)
to 1.
When a GPIO is enabled as a push/pull output, the value output to the GPIO pin is set via the
corresponding
(GPIO_DATA_DIR). For GPIOs configured as inputs, the corresponding
bit reflects the current state of the GPIO input.
GPIO Interrupts
Each GPIO provides the ability to trigger a unique GPIO interrupt in the
Status and Enable Register
bits of this register provides the current status of the corresponding interrupt, and each interrupt is
enabled by setting the corresponding
GPIO/LED Controller aggregates the enabled interrupt values into an internal signal that is sent to the
System Interrupt Controller and is reflected via the
Event (GPIO)
page
Functional Overview
GPIO Operation
All GPIOs are set as inputs
& Direction Register
All GPIO interrupts are disabled
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
All GPIO interrupts are configured to low logic level triggering
(GPIO_INT_POL[5:0])
55.
configuration straps. Refer to
GPIO Data 5-0 (GPIOD[5:0])
bit. For more information on interrupts, refer to
bit in the
bits in the
and
(GPIO_DATA_DIR))
General Purpose I/O Data & Direction Register
cleared in
General Purpose I/O Data & Direction Register
(GPIO_INT_STS_EN). Reading the
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
General Purpose I/O Configuration Register
(GPIO Direction 5-0 (GPDIR[5:0])
DATASHEET
(GPIO Interrupt Enable[5:0] (GPIO[5:0]_INT_EN)
General Purpose I/O Configuration Register
Section 12.3, "LED Operation"
Section 13.2.2, "GPIO/LED," on page
GPIO Interrupt Enable[5:0] (GPIO[5:0]_INT_EN)
132
bit in the
Interrupt Status Register (INT_STS) GPIO Interrupt
General Purpose I/O Data & Direction Register
GPIO Data 5-0 (GPIOD[5:0])
is cleared to 0, and is not driven when set
cleared in
GPIO Interrupt[5:0] (GPIO[5:0]_INT)
Chapter 5, "System Interrupts," on
(GPIO Interrupt Polarity 5-0
General Purpose I/O Configuration
for additional information.
General Purpose I/O Interrupt
GPIO Data 5-0 (GPIOD[5:0])
(GPIO_CFG). Push/pull and
General Purpose I/O Data
(GPIO_DATA_DIR). When
(GPIO_DATA_DIR). The
144.
SMSC LAN9303/LAN9303i
GPIO Buffer Type 5-
(GPIO_CFG))
LED_en_strap[5:0]
GPIO Direction 5-
bit in the
cleared in
Datasheet
bit. The
General