LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 25

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
PINS
PINS
NUM
NUM
1
2
2
1
1
1
1
Port 0 MII Input
Bias Reference
Analog Power
Analog Power
+3.3V Master
+3.3V Port 1
+3.3V Port 2
+1.8V Power
+1.8V Power
Bias Power
Transmitter
Transmitter
Note 3.2
Note 3.3
Supply
Supply
Supply
Supply
Supply
NAME
NAME
Data 3
Port 2
Port 1
The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected or manually selected, the RX and TX pins
will be swapped internally.
Please refer to the LAN9303/LAN9303i Reference Schematic and LANCheck Schematic
Checklist on the SMSC website for additional connection information.
Table 3.3 LAN Port 1 & 2 Power and Common Pins
VDD33BIAS
VDD18TX2
VDD18TX1
VDD33A1
VDD33A2
SYMBOL
SYMBOL
P0_IND3
EXRES
Table 3.4 Port 0 MII/RMII Pins
DATASHEET
BUFFER
BUFFER
TYPE
TYPE
(PD)
(PD)
AI
IS
IS
P
P
P
P
P
-
25
Used for internal bias circuits. Connect to an
external 12.4K ohm, 1% resistor to ground.
See
See
See
This pin is supplied from the internal PHY voltage
regulator. This pin must be tied to the VDD18TX1
pin for proper operation.
See
This pin must be connected directly to the
VDD18TX2 pin for proper operation.
See
MII MAC Mode: This pin is the receive data 3 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 3 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the
(VPHY_ISO)
Control Register
RMII PHY Mode: This pin is not used.
Note
Note
Note
Note
Note
3.3.
3.3.
3.3.
3.3.
3.3.
bit is set in the
(VPHY_BASIC_CTRL).
DESCRIPTION
DESCRIPTION
Virtual PHY Basic
Revision 1.4 (07-07-10)
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