LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 289

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.4.3.16
31:16
12:10
BITS
15
14
13
9
8
7
6
5
4
3
RESERVED
802.1Q VLAN Disable
When set, the VID from the VLAN tag is ignored and the per port default
VID (PVID) is used for purposes of VLAN rules. This does not affect the
packet tag on egress.
Use Tag
When set, the priority from the VLAN tag is enabled as a transmit priority
queue choice.
Allow Monitor Echo
When set, monitoring packets are allowed to be echoed back to the source
port. When cleared, monitoring packets, like other packets, are never sent
back to the source port.
This bit is useful when the monitor port wishes to receive it’s own IGMP
packets.
IGMP Monitor Port
This field is the port bit map where IPv4 IGMP packets are sent.
Use IP
When set, the IPv4 TOS or IPv6 SC field is enabled as a transmit priority
queue choice.
RESERVED
Enable IGMP Monitoring
When set, IPv4 IGMP packets are monitored and sent to the IGMP monitor
port.
SWE Counter Test
When this bit is set the Switch Engine counters that normally clear to 0 when
read will be set to 7FFF_FFFCh when read.
DA Highest Priority
When this bit is set and the priority enable bit in the ALR table for the
destination MAC address is set, the transmit priority queue that is selected
is taken from the ALR Priority bits (see the
1 Register
Filter Multicast
When this bit is set, packets with a multicast destination address are filtered
if the address is not found in the ALR table. Broadcasts are not included in
this filter.
Drop Unknown
When this bit is set, packets with a unicast destination address are filtered
if the address is not found in the ALR table.
Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)
This register is used to configure the global ingress rules.
(SWE_ALR_RD_DAT_1)).
Register #:
1840h
DESCRIPTION
DATASHEET
Switch Engine ALR Read Data
289
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Revision 1.4 (07-07-10)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
-
-