LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 355
LAN9303I-ABZJ
Manufacturer Part Number
LAN9303I-ABZJ
Description
Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
Manufacturer
SMSC
Datasheet
1.LAN9303-ABZJ.pdf
(367 pages)
Specifications of LAN9303I-ABZJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
14.5.5
SYMBOL
t
t
t
t
t
hold
clkp
clkh
clkl
val
P0_OUTD[3:0]
P0_OUTCLK
P0_OUTDV
MII Interface Timing (PHY Mode)
This section specifies the MII interface input and output timing when in PHY mode. Please refer to
Chapter 9, "MII Data Interface," on page 121
Note 14.14 Timing was designed for system load between 10 pf and 25 pf.
P0_OUTCLK period
P0_OUTCLK high time
P0_OUTCLK low time
P0_OUTD[3:0], P0_OUTDV output valid from
rising edge of P0_OUTCLK
P0_OUTD[3:0], P0_OUTDV output hold from
rising edge of P0_OUTCLK
(output)
Table 14.11 MII Output Timing Values (PHY Mode)
DESCRIPTION
Figure 14.6 MII Output Timing (PHY Mode)
t
hold
DATASHEET
t
val
t
clkh
355
t
clkp
for additional details.
t
clkl
t
t
clkp
clkp
10.0
t
MIN
val
40
*0.4
*0.4
t
t
clkp
clkp
MAX
28.0
*0.6
*0.6
t
hold
UNITS
Revision 1.4 (07-07-10)
ns
ns
ns
ns
ns
t
val
Note 14.14
Note 14.14
NOTES
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