LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 149

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
30:28
27:19
BITS
18
17
EEPROM Controller Command (EPC_COMMAND)
This field is used to issue commands to the EEPROM controller. The
EEPROM controller will execute a command when the EPC_BUSY bit is set.
A new command must not be issued until the previous command completes.
The field is encoded as follows:
Note:
The EEPROM operations are defined as follows:
READ (Read Location)
This command will cause a read of the EEPROM location pointed to by the
EPC_ADDRESS bit field. The result of the read is available in the
Data Register
WRITE (Write Location)
If erase/write operations are enabled in the EEPROM, this command will
cause the contents of the
to the EEPROM location selected by the EPC_ADDRESS field.
RELOAD (EEPROM Loader Reload)
Instructs the EEPROM Loader to reload the device from the EEPROM. If a
value of A5h is not found in the first address of the EEPROM, the EEPROM
is assumed to be un-programmed and the RELOAD operation will fail. The
CFG_LOADED bit indicates a successful load. Following this command, the
device will enter the not ready state. The
Hardware Configuration Register (HW_CFG)
when the RELOAD is complete.
RESERVED
EEPROM Loader Address Overflow (LOADER_OVERFLOW)
This bit indicates that the EEPROM Loader tried to read past the end of the
EEPROM address space. This indicates misconfigured EEPROM data.
This bit is cleared when the EEPROM Loader is restarted with a RELOAD
command, or a
EEPROM Controller Timeout (EPC_TIMEOUT)
This bit is set when a timeout occurs, indicating the last operation was
unsuccessful. If an EEPROM WRITE operation is performed, and no
response is received from the EEPROM within 30mS, the EEPROM
controller will timeout and return to its idle state.
The bit is also set if the EEPROM fails to respond with the appropriate
ACKs, if the EEPROM slave device holds the clock low for more than 30mS,
if the I
EPC_COMMAND is attempted.
This bit is cleared when written high.
2
[30]
C bus is not acquired within 1.92 seconds, or if an unsupported
0
0
0
0
1
1
1
1
Only the READ, WRITE and RELOAD commands are valid for I
mode. If an unsupported command is attempted, the EPC_BUSY
bit will be cleared and EPC_TIMEOUT will be set.
(E2P_DATA).
Digital Reset
[29]
0
0
1
1
0
0
1
1
EEPROM Data Register (E2P_DATA)
(DIGITAL_RST).
DESCRIPTION
[28]
0
1
0
1
0
1
0
1
DATASHEET
Device Ready (READY)
149
should be polled to determine
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Operation
RELOAD
WRITE
READ
to be written
EEPROM
bit in the
2
C
TYPE
R/WC
R/W
RO
RO
Revision 1.4 (07-07-10)
DEFAULT
000b
0b
0b
-