LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 99

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
7.2.6
7.2.7
In full-duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS
responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is
disabled.
HP Auto-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP
interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct
connect LAN cable or a cross-over patch cable, as shown in
the PHY is capable of configuring the TXPx/TXNx and RXPx/RXNx twisted pair pins for correct
transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled through the
x PHY Special Control/Status Indication Register
Auto-MDIX Control (AMDIXCTRL)
configuration straps
The MDIX can also be configured manually via the Manual MDIX strap
manual_mdix_strap_2
bit and the Auto-MDIX Enable configuration strap are low. Refer to
page 24
When the
Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
by the
Special Control/Status Indication Register
MII MAC Interface
The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and
from the Switch Fabric MAC. The PHY is connected internally to the Switch Fabric MAC via standard
MII signals per IEEE 802.3.
For a transmission, the Switch Fabric MAC drives the transmit data onto the internal MII TXD bus and
asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for
100BASE-TX, or 2.5MHz for 10BASE-T.
Not Used
Not Used
Not Used
Not Used
RXNx
TXNx
RXPx
TXPx
Figure 7.4 Direct Cable Connection vs. Cross-Over Cable Connection
Auto-MDIX Enable (AMDIXEN)
for more information on the configuration straps.
Auto-MDIX Control (AMDIXCTRL)
RJ-45 8-pin straight-through
1
2
3
4
5
6
7
8
for 10BASE-T/100BASE-TX
Direct Connect Cable
signaling
(auto_mdix_strap_1
for Port 1 and Port 2, respectively) if both the
1
2
3
4
5
6
7
8
TXPx
TXNx
RXPx
Not Used
Not Used
RXNx
Not Used
Not Used
DATASHEET
is cleared, Auto-MDIX can be selected via the Auto-MDIX Enable
and
and
(PHY_SPECIAL_CONTROL_STAT_IND_x).
99
Auto-MDIX State (AMDIXSTATE)
auto_mdix_strap_2
bit of the
Not Used
Not Used
Not Used
Not Used
RXPx
RXNx
TXPx
TXNx
(PHY_SPECIAL_CONTROL_STAT_IND_x). When
is set to 1, the Auto-MDIX capability is determined
Auto-MDIX Control (AMDIXCTRL)
Port x PHY Special Control/Status Indication
1
2
3
4
5
6
7
8
RJ-45 8-pin cross-over for
10BASE-T/100BASE-TX
Cross-Over Cable
signaling
Figure 7.4
for Port 1 and Port 2, respectively).
Section 3.2, "Pin Descriptions," on
Auto-MDIX Control (AMDIXCTRL)
(
(manual_mdix_strap_1
See
1
2
3
4
5
6
7
8
TXPx
TXNx
RXPx
Not Used
Not Used
RXNx
Not Used
Not Used
bits of the
Note 7.1 on page 89
Revision 1.4 (07-07-10)
bit of the
Port x PHY
Port
and
)
,