LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 191

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.3
13.3.1
13.3.2
INDEX #
0
1
2
3
4
5
6
This section details the various Ethernet PHY control and status registers. The device contains three
PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers follow the IEEE 802.3 (clause
22.2.4) specified MII management register set. All functionality and bit definitions comply with these
standards. The IEEE 802.3 specified register index (in decimal) is included with each register definition,
allowing for addressing of these registers via the MII serial management protocol. For additional
information on the MII management protocol, refer to the IEEE 802.3 Specification.
Each individual PHY is assigned a unique PHY address as detailed in
Addressing," on page
Virtual PHY Registers
The Virtual PHY provides a basic MII management interface for communication with an standard
external MAC as if it was attached to a single port PHY. The Virtual PHY registers differ from the Port
1 & 2 PHY registers in that they are addressable via the memory map, as described in
well as serially. These modes of access are described in
Because the Virtual PHY registers are also memory mapped, their definitions have been included in
the
PHY MII addressable registers and their corresponding register index numbers is also included in
Table
Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII
Port 1 & 2 PHY Registers
The Port 1 and Port 2 PHY’s are comparable in functionality and have an identical set of non-memory
mapped registers. The Port 1 and Port 2 PHY registers are not memory mapped. These registers are
indirectly accessed through the
Management Interface Data Register (PMI_DATA)
through the MII management pins (in MAC or PHY SMI modes only) via the MII serial management
protocol specified in IEEE 802.3 clause 22. See
details on the various device modes. Because the Port 1 & 2 PHY registers are functionally identical,
their register descriptions have been consolidated. A lowercase “x” has been appended to the end of
each PHY register name in this section, where “x” should be replaced with “1” or “2” for the Port 1
PHY or the Port 2 PHY registers respectively. A list of the Port 1 & 2 PHY MII addressable registers
and their corresponding register index numbers is included in
assigned a unique PHY address as detailed in
Ethernet PHY Control and Status Registers
System Control and Status Registers Section 13.2.6, "Virtual PHY," on page
PHY_BASIC_CONTROL_x
13.5.
PHY_AN_LP_BASE_ABILITY_x
PHY_BASIC_STATUS_x
management of PHY’s.
PHY_AN_ADV_x
PHY_AN_EXP_x
PHY_ID_MSB_x
PHY_ID_LSB_x
Table 13.8 Port 1 & 2 PHY MII Serially Adressable Registers
SYMBOL
88.
PHY Management Interface Access Register (PMI_ACCESS)
DATASHEET
Port x PHY Basic Control Register,
Port x PHY Identification MSB Register,
Port x PHY Identification LSB Register,
Port x PHY Auto-Negotiation Advertisement Register,
Section 13.3.2.5
Port x PHY Auto-Negotiation Link Partner Base Page Ability
Register,
Port x PHY Auto-Negotiation Expansion Register,
Section 13.3.2.7
Port x PHY Basic Status Register,
191
Section 13.3.2.6
Section 7.1.1, "PHY Addressing," on page
Section 2.3, "Modes of Operation," on page 19
registers (in MAC or PHY I
Section 13.2.6, "Virtual PHY," on page
REGISTER NAME
Table
13.8. Each individual PHY is
Section 13.3.2.2
Section 13.3.2.1
Section 13.3.2.4
Section 13.3.2.3
169. A list of the Virtual
Section 7.1.1, "PHY
Revision 1.4 (07-07-10)
2
C modes only) or
Table
88.
and
13.2, as
169.
for a
PHY