LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 182

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.4 (07-07-10)
13.2.6.8
31:16
13:11
BITS
9:8
15
14
10
7
6
5
RESERVED
(See
RESERVED
Switch Looopback Port 0
When set, transmissions from the Switch Fabric Port 0 are not sent to the
External MAC. Instead, they are looped back into the Switch Engine.
From the MAC viewpoint, this is effectively a FAR LOOPBACK.
If loopback is enabled during half-duplex operation, then the
Own Transmit
(MAC_RX_CFG_x)
will ignore receive activity when transmitting in half-duplex mode.
Note:
RESERVED
Turbo MII Enable
When set, this bit changes the data rate of the MII PHY 100Mbps mode to
200Mbps. The normal Virtual PHY selection mechanism that chooses
between 10 and 100Mbps will instead choose between 10Mbps and
200Mbps.
Note:
Mode
This field indicates the operating mode of port 0.
00: MII MAC mode
01: MII PHY mode
10: RMII PHY mode
11: RESERVED
Switch Collision Test Port 0
When set, the collision signal to the Switch Fabric Port 0 is active during
transmission from the Switch Engine.
Note:
RMII Clock Direction
0: Selects P0_OUTCLK as an Input
1: Selects P0_OUTCLK as an Output
RMII/Turbo MII Clock Strength
For RMII and 200 Mbps MII PHY modes, a low selects 12 mA drive while a
high selects a 16 mA drive. For 100 Mbps and 10 Mbps MII PHY modes,
the drive strength is fixed at 12mA.
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
This read/write register contains a current link speed/duplex indicator and SQE control.
Note
This mode works even if the
PHY Basic Control Register (VPHY_BASIC_CTRL)
When operating at 200Mbps, the drive strength of the MII output
clocks is selected using the
When at 100 Mbps or 10 Mbps, the drive strength is fixed at 12
mA.
It is recommended that this bit be used only when using loopback
mode.
13.44)
Offset:
Index (decimal):
bit in the
must be set for this port. Otherwise, the Switch Fabric
Port x MAC Receive Configuration Register
1DCh
31
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
RMII/Turbo MII Clock Strength
DATASHEET
Isolate (VPHY_ISO)
182
Size:
bit of the
Enable Receive
is set.
32 bits
Virtual
bit.
Note 13.50
Note 13.50
NASR
NASR
TYPE
R/W
R/W
R/W
R/W
R/W
SMSC LAN9303/LAN9303i
RO
RO
RO
RO
Note 13.45
Note 13.46
Note 13.47
Note 13.48
DEFAULT
Datasheet
0b
0b
-
-
-