LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 64

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.4 (07-07-10)
6.3
6.3.1
Per
The Switch Fabric contains three 10/100 MAC blocks, one for each switch port (0,1,2). The 10/100
MAC provides the basic 10/100 Ethernet functionality, including transmission deferral and collision
back-off/retry, receive/transmit FCS checking and generation, receive/transmit pause flow control, and
transmit back pressure. The 10/100 MAC also includes RX and TX FIFOs and per port statistic
counters.
Receive MAC
The receive MAC (IEEE 802.3) sublayer decomposes Ethernet packets acquired via the internal MII
interface by stripping off the preamble sequence and Start of Frame Delimiter (SFD). The receive MAC
checks the FCS, the MAC Control Type, and the byte count against the drop conditions. The packet
is stored in the RX FIFO as it is received.
The receive MAC determines the validity of each received packet by checking the Type field, FCS, and
oversize or undersize conditions. All bad packets will be either immediately dropped or marked (at the
end) as bad packets.
Oversized packets are normally truncated at 1519 or 1523 (VLAN tagged) octets and marked as
erroneous. The MAC can be configured to accept packets up to 2048 octets (inclusive), in which case
the oversize packets are truncated at 2048 bytes and marked as erroneous.
Undersized packets are defined as packets with a length less than the minimum packet size. The
minimum packet size is defined to be 64 bytes, exclusive of preamble sequence and SFD.
The FCS and length/type fields of the frame are checked to detect if the packet has a valid MAC
control frame. When the MAC receives a MAC control frame with a valid FCS and determines the
operation code is a pause command (Flow Control frame), the MAC will load its internal pause counter
with the Number_of_Slots variable from the MAC control frame just received. Anytime the internal
pause counter is zero, the transmit MAC will be allowed to transmit (XON). If the internal pause counter
is not zero, the receive MAC will not allow the transmit MAC to transmit (XOFF). When the transmit
MAC detects an XOFF condition it will continue to transmit the current packet, terminating transmission
after the current packet has been transmitted until receiving the XON condition from the receive MAC.
The pause counter will begin to decrement at then end of the current transmission, or immediately if
no transmission is underway. If another pause command is received while the transmitter is already in
pause, the new pause time indicated by the Flow Control packet will be loaded into the pause counter.
The pause function is enabled by either Auto-negotiation, or manually as discussed in
10/100 Ethernet MACs
Case 1 - Auto-negotiation is still in progress. Since the result is not yet established, flow control is
disabled.
Case 2 - Auto-negotiation is enabled and unsuccessful (link partner not Auto-negotiation capable).
The link partner ability is undefined, effectively a don’t-care value, in this case. The duplex setting
will default to half-duplex in this case. Flow control is determined by the BP_EN_x bit.
Case 3 - Auto-negotiation is enabled and successful with half-duplex as a result. The link partner
ability is undefined since it only applies to full-duplex operation. Flow control is determined by the
BP_EN_x bit.
Cases 4-11 -Auto-negotiation is enabled and successful with full-duplex as the result. In these
cases, the advertisement registers and the link partner ability controls the RX and TX enables.
These cases match IEEE 802.3 Annex 28B.3.
Table
Cases 4,5,6,8,10 - No flow control enabled
Case 7 - Asymmetric pause towards partner (away from switch port)
Case 9 - Symmetric pause
Case 11 - Asymmetric pause from partner (towards switch port)
6.1, the following cases are possible:
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
64
SMSC LAN9303/LAN9303i
Section 6.2.3,
Datasheet