LAN9311I-NZW Standard Microsystems (SMSC), LAN9311I-NZW Datasheet - Page 111

• Manufacturer Part Number: LAN9311I-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311I-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
8.5.8
D[15:0] (INPUT)
PIO Writes
PIO writes are used for all LAN9311/LAN9311i write cycles. PIO writes can be performed using Chip
Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted.
The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control
signals must de-assert between cycles for the period specified in
Values,” on page
control signals must be de-asserted between cycles for the period specified. The PIO write cycle is
illustrated in the functional timing diagram in
The END_SEL signal has the same timing characteristics as the address lines.
Please refer to
for PIO write operations.
nCS, nWR
END_SEL
A[x:1]
Figure 8.7 Functional Timing for PIO Write Operation
Section 15.5.8, "PIO Write Cycle Timing," on page 451
451. They may be asserted and de-asserted in any order. Either or both of these
DATASHEET
111
Figure
VALID
VALID
8.7.
VALID
Table 15.12, “PIO Write Cycle Timing
for the AC timing specifications
Revision 1.7 (06-29-10)