LAN9311I-NZW Standard Microsystems (SMSC), LAN9311I-NZW Datasheet - Page 306

• Manufacturer Part Number: LAN9311I-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311I-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.7 (06-29-10)
14.4.2.11
BITS
15:8
7
6
5
4
3
2
1
0
RESERVED
INT7
This interrupt source bit indicates when the ENERGYON bit of the
PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
has been set.
0: Not source of interrupt
1: ENERGYON generated
INT6
This interrupt source bit indicates Auto-Negotiation is complete.
0: Not source of interrupt
1: Auto-Negotiation complete
INT5
This interrupt source bit indicates a remote fault has been detected.
0: Not source of interrupt
1: Remote fault detected
INT4
This interrupt source bit indicates a Link Down (link status negated).
0: Not source of interrupt
1: Link Down (link status negated)
INT3
This interrupt source bit indicates an Auto-Negotiation LP acknowledge.
0: Not source of interrupt
1: Auto-Negotiation LP acknowledge
INT2
This interrupt source bit indicates a Parallel Detection fault.
0: Not source of interrupt
1: Parallel Detection fault
INT1
This interrupt source bit indicates an Auto-Negotiation page received.
0: Not source of interrupt
1: Auto-Negotiation page received
RESERVED
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
This read-only register is used to determine to source of various Port x PHY interrupts. All interrupt
source bits in this register are read-only and latch high upon detection of the corresponding interrupt
(if enabled). A read of this register clears the interrupts. These interrupts are enabled or masked via
the
Port x PHY Interrupt Mask Register
Index (decimal): 29
DESCRIPTION
DATASHEET
(PHY_INTERRUPT_MASK_x).
306
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
16 bits
Port x
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
TYPE
SMSC LAN9311/LAN9311i
RO
RO
DEFAULT
Datasheet
0b
0b
0b
0b
0b
0b
0b
-
-