AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 108

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4
3
2
108
TXON
TDMD
STOP
Read accessible always. RXON
is read only. RXON is cleared by
H_RESET or S_RESET and set-
ting the STOP bit.
This bit will reset if the DXSUFLO
bit (CSR3, bit 6) is reset and there
is an underflow condition encoun-
tered.
Read accessible always. TXON
is read only. TXON is cleared by
H_RESET or S_RESET and set-
ting the STOP bit.
TDMD is required to be set if the
TXDPOLL bit in CSR4 is set. Set-
ting TDMD while TXDPOLL = 0
merely hastens the Am79C972
controller’s response to a Trans-
mit Descriptor Ring Entry.
Read/Write accessible always.
TDMD is set by writing a 1. Writ-
ing a 0 has no effect. TDMD will
be cleared by the Buffer Manage-
ment Unit when it fetches a
Transmit Descriptor. TDMD is
cleared
S_RESET and setting the STOP
bit.
RXON will not be set until after
the initialization block has been
read in.
Transmit On indicates that the
transmit function is enabled.
TXON is set if DTX (CSR15, bit 1)
is set to 0 after the START bit is
set. If INIT and START are set to-
gether, TXON will not be set until
after the initialization block has
been read in.
Transmit Demand, when set,
causes the Buffer Management
Unit to access the Transmit De-
scriptor Ring without waiting for
the poll-time counter to elapse. If
TXON is not enabled, TDMD bit
will be reset and no Transmit De-
scriptor Ring access will occur.
STOP assertion disables the chip
from all DMA activity. The chip re-
mains inactive until either STRT
or INIT are set. If STOP, STRT
and INIT are all set together,
by
H_RESET
Am79C972
or
1
0
CSR1: Initialization Block Address 0
Bit
31-16 RES
15-0
STRT
INIT
Name
IADR[15:0] Lower 16 bits of the address of
STOP will override STRT and
INIT.
Read/Write accessible always.
STOP is set by writing a 1, by
H_RESET or S_RESET. Writing
a 0 has no effect. STOP is
cleared by setting either STRT or
INIT.
Am79C972 controller to send and
receive frames, and perform buff-
er management operations. Set-
ting STRT clears the STOP bit. If
STRT and INIT are set together,
the Am79C972 controller initial-
ization will be performed first.
Read/Write accessible always.
STRT is set by writing a 1. Writing
a 0 has no effect. STRT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
Am79C972 controller to begin the
initialization
reads in the initialization block
from memory. Setting INIT clears
the STOP bit. If STRT and INIT
are set together, the Am79C972
controller initialization will be per-
formed first. INIT is not cleared
when the initialization sequence
has completed.
Read/Write accessible always.
INIT is set by writing a 1. Writing
a 0 has no effect. INIT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
zeros and read as undefined.
the Initialization Block. Bit loca-
tions 1 and 0 must both be 0 to
align the initialization block to a
DWord boundary.
This register is aliased with
CSR16.
STRT
INIT
Description
Reserved locations. Written as
assertion
assertion
procedure
enables
enables
which
the