AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 112

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CSR4: Test and Features Control
Certain bits in CSR4 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR4 and write back
the value just read to clear the interrupt condition.
Bit
31-16
15
14
13
12
11
112
APAD_XMT Auto Pad Transmit. When set,
Name
RES
RES
DMAPLUS Writing and reading from this bit
RES
TXDPOLL
Read/Write accessible always.
This bit is cleared by H_RESET
or S_RESET and is unaffected by
the STOP bit.
Read/Write accessible always.
TXDPOLL
H_RESET or S_RESET and is
unaffected by the STOP bit.
should write a 0 to this bit and
should treat the read value as un-
defined.
Description
Reserved locations. Written as
zeros and read as undefined.
Reserved location. It is OK for
legacy software to write a 1 to this
location. This bit must be set
back to 0 before setting INIT or
STRT bits.
has no effect. DMAPLUS is al-
ways set to 1.
Reserved Location. Written as
zero and read as undefined.
Disable Transmit Polling. If TXD-
POLL is set, the Buffer Manage-
ment Unit will disable transmit
polling. Likewise, if TXDPOLL is
cleared, automatic transmit poll-
ing is enabled. If TXDPOLL is set,
TDMD bit in CSR0 must be set in
order to initiate a manual poll of a
transmit descriptor. Transmit de-
scriptor polling will not take place
if TXON is reset. Transmit polling
will take place following Receive
activities.
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes including FCS.
The FCS is calculated for the en-
is
cleared
Am79C972
by
10
9
8
7
ASTRP_RCV Auto Strip Receive. When set,
MFCO
MFCOM
UINTCMD
tire frame, including pad, and ap-
pended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15, bit 3) and of the
ADD_FCS bit (TMD1, bit 29) for
frames shorter than 64 bytes.
Read/Write accessible always.
APAD_XMT
H_RESET or S_RESET and is
unaffected by the STOP bit.
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
Read/Write accessible always.
ASTRP_RCV
H_RESET or S_RESET and is
unaffected by the STOP bit.
is set by the Am79C972 control-
ler when the Missed Frame
Counter (CSR112 and CSR114)
has wrapped around.
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
Read/Write accessible always.
MFCO is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
Read/Write accessible always.
MFCOM is set to 1 by H_RESET
or S_RESET and is not affected
by the STOP bit.
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1.
Missed Frame Counter Overflow
Missed Frame Counter Overflow
User
MFCO
Interrupt
is
is
is
cleared
cleared
cleared
Command.
by
by
by