AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 113

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6
5
4
3
UINT
RCVCCO
RCVCCOM Receive Collision Counter Over-
TXSTRT
Read/Write accessible always.
UINTCMD
H_RESET or S_RESET or by
setting the STOP bit.
Read/Write accessible always.
UINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET or S_RESET or by
setting the STOP bit.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Read/Write accessible always.
RCVCCO is cleared by the host
by writing a 1. Writing a 0 has no
effect. RCVCCO is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible always.
RCVCCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
Read/Write accessible always.
TXSTRT is cleared by the host by
writing a 1. Writing a 0 has no ef-
Writing a 1 to UNIT will clear
UNITCMD and stop interrupts.
User Interrupt. UINT is set by the
Am79C972 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
Receive Collision Counter Over-
flow is set by the Am79C972 con-
troller when the Receive Collision
Counter (CSR114 and CSR115)
has wrapped around.
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Transmit Start status is set by the
Am79C972 controller whenever it
begins transmission of a frame.
UINT
is
is
cleared
cleared
Am79C972
by
by
2
1-0
CSR5: Extended Control and Interrupt 1
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR5 and write back
the value just read to clear the interrupt condition.
Bit
31-16 RES
15
14
TXSTRTM
RES
Name
TOKINTD
LTINTEN
fect. TXSTRT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
Read/Write accessible always.
TXSTRTM
H_RESET or S_RESET and is
not affected by the STOP bit.
zeros and read as undefined.
zeros and read as undefined.
TOKINTD is set to 1, the TINT bit
in CSR0 will not be set when a
transmission
Only a transmit error will set the
TINT bit.
TOKINTD has no effect when
LTINTEN (CSR5, bit 14) is set to
1. A transmit descriptor with
LTINT set to 1 will always cause
TINT to be set to 1, independent
of the success of the transmis-
sion.
Read/Write accessible always.
TOKINTD
H_RESET or S_RESET and is
unaffected by STOP.
When set to 1, the LTINTEN bit
will cause the Am79C972 control-
ler to read bit 28 of TMD1 as
LTINT. The setting LTINT will de-
termine if TINT will be set at the
end of the transmission.
Transmit Start Mask. If TX-
Reserved locations. Written as
Description
Reserved locations. Written as
Transmit OK Interrupt Disable. If
Last Transmit Interrupt Enable.
is
is
was
set
cleared
successful.
to
1
113
by
by