AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 87

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

There are two general methods to place the PCnet-
FAST+ into the Magic Packet mode. The first is the soft-
ware method. In this method, either the BIOS or other
software, sets the MPMODE bit (CSR5, bit 1). Then
PCnet-FAST+ controller must be put into suspend
mode (see description of CSR5, bit 0), allowing any
current network activity to finish. Finally, either PG must
be deasserted (hardware control) or MPEN (CSR5, bit
2) must be set to 1 (software control).
Note: FASTSPNDE (CSR7, bit 15) has no meaning in
Magic Packet mode.
The second method is the hardware method. In this
method, the MPPEN bit (CSR116, bit 4) is set at power
up by the loading of the EEPROM. This bit can also be
set by software. The PCnet-FAST+ will be placed in the
BCR Bit Number 15
Pattern Match
RAM Address
J+m
2+n
63
0
1
2
J
39
Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern P
Data Byte 4n+3
Data Byte 3
Data Byte 3
P3 pointer
P7 pointer
PMR_B4
32 31
BCR 47
8
7
Date Byte 4n+2
Data Byte 2
Data Byte 2
P2 pointer
P6 pointer
PMR_B3
Figure 49. Pattern Match RAM
Pattern Match RAM Bit Number
24
0 15
Data Byte 4n+1
23
Am79C972
Data Byte 1
Data Byte1
P1 pointer
P5 pointer
PMR_B2
Magic Packet Mode when either the PG input is
deasserted or the MPEN bit is set. WUMI output will be
asserted when the PCnet-FAST+ is in the Magic
Packet mode. Magic Packet mode can be disabled at
any time by asserting PG or clearing MPEN bit.
When the PCnet-FAST+ controller detects a Magic
Packet frame, it sets the MPMAT bit (CSR116, bit 5),
the MPINT bit (CSR5, bit 4), and the PME_STATUS bit
(PMCSR, bit 15). The setting of the MPMAT bit will also
cause the RWU pin to be asserted and if the PME_EN
or the PME_EN_OVR bits are set, then the PME will be
asserted as well. If IENA (CSR0, bit 6) and MPINTE
(CSR5, bit 3) are set to 1, INTA will be asserted. Any
one of the four LED pins can be programmed to indi-
cate that a Magic Packet frame has been received.
BCR 46
8
16
Data Byte 4n+0
7
15
Data Byte 0
Data Byte 0
P0 pointer
P4 pointer
PMR_B1
7
EOP
6
8
0 15
5
SKIP
7
Pattern Control
Pattern Control End Pattern P
Pattern Control Start Pattern P
Pattern Enable
PMR_B0
BCR 45
4
bits
X
3
2
0
8
MASK
1
First Address
Last Address
Start Pattern
21485C-52
Comments
Address
Second
0
P
1
87
1
k
k