AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 88

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

MPSE (BCR4-7, bit 9) must be set to 1 to enable that
function.
Note: The polarity of the LED pin can be programmed
to be active HIGH by setting LEDPOL (BCR4-7, bit 14)
to 1.
Once a Magic Packet frame is detected, the PCnet-
FAST+ controller will discard the frame internally, but
will not resume normal transmit and receive operations
until PG is asserted or MPEN is cleared. Once both of
these events has occurred, indicating that the system
has detected the Magic Packet and is awake, the con-
troller will continue polling receive and transmit de-
scriptor rings where it left off. It is not necessary to re-
initialize the device. If the part is reinitialized, then the
descriptor locations will be reset and the PCnet-FAST+
controller will not start where it left off.
If magic packet mode is disabled by the assertion of
PG, then in order to immediately re-enable Magic
Packet mode, the PG pin must remain asserted for at
least 200 ns before it is deasserted. If Magic Packet
mode is disabled by clearing MPEN bit, then it may be
immediately re-enabled by setting MPEN back to 1.
The PCI bus interface clock (CLK) is not required to be
running while the device is operating in Magic Packet
mode. Either of the INTA, the LED pins, RWU or the
PME signal may be used to indicate the receipt of a
Magic Packet frame when the CLK is stopped. If the
system wishes to stop the CLK, it will do so after en-
abling the Magic Packet mode.
CAUTION: To prevent unwanted interrupts from other
active parts of the PCnet-FAST+ controller, care must
be taken to mask all likely interruptible events during
Magic Packet mode. An example would be the inter-
rupts from the Media Independent Interface, which
could occur while the device is in Magic Packet mode.
IEEE 1149.1 (1990) Test Access Port
Interface
An IEEE 1149.1-compatible boundary scan Test Ac-
cess Port is provided for board-level continuity test and
diagnostics. All digital input, output, and input/output
pins are tested. The following paragraphs summarize
the IEEE 1149.1-compatible test functions imple-
mented in the Am79C972 controller.
Boundary Scan Circuit
The boundary scan test circuit requires four pins (TCK,
TMS, TDI, and TDO), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
struction register, a data register array, and a power-on
reset circuit. Internal pull-up resistors are provided for
the TDI, TCK, and TMS pins.
TAP Finite State Machine
The TAP engine is a 16-state finite state machine
(FSM), driven by the Test Clock (TCK), and the Test
88
Am79C972
Mode Select (TMS) pins. An independent power-on
reset circuit is provided to ensure that the FSM is in the
TEST_LOGIC_RESET state at power-up. Therefore,
the TRST is not provided. The FSM is also reset when
TMS and TDI are high for five TCK periods.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP, and SET-
BYP) are provided to further ease board-level testing.
All unused instruction codes are reserved. See Table
12 for a summary of supported instructions.
Instruction Register and Decoding Logic
After the TAP FSM is reset, the IDCODE instruction is
always invoked. The decoding logic gives signals to con-
trol the data flow in the Data registers according to the
current instruction.
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two
stages. A flip-flop and a latch are used for the Serial
Shift Stage and the Parallel Output Stage, respectively.
There are four possible operation modes in the BSR
cell shown in Table 13.
Instructio
SAMPLE
EXTEST
IDCODE
SETBYP
BYPASS
TRIBYP
Table 12. IEEE 1149.1 Supported Instruction
Name
1
2
3
4
n
Table 13. BSR Mode Of Operation
Capture
Shift
Update
System Function
Instructi
Code
0000
0001
0010
0011
0100
1111
on
External Test
ID Code
Inspection
Sample
Boundary
Force Float
Control
Boundary To
1/0
Bypass Scan Normal
Summary
Description
Normal
Normal
Normal
Mode
Test
Test
Selected
Register
ID REG
Bypass
Bypass
Bypass
Data
BSR
BSR