AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 89

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Other Data Registers
Other data registers are the following:
1. Bypass Register (1 bit)
2. Device ID register (32 bits) (Table 14).
Note: The content of the Device ID register is the
same as the content of CSR88.
NAND Tree Testing
The Am79C972 controller provides a NAND tree test
mode to allow checking connectivity to the device on a
printed circuit board. The NAND tree is built on all PCI
bus, TBC_EN, and EAR pins.
NAND tree testing is enabled by asserting RST. PG
input should be driven HIGH during NAND tree testing.
All PCI bus signals will become inputs on the assertion
Bits 31-28
Bits 27-12
Bits 11-1
Bit 0
RST (pin143)
CLK (pin 144)
GNT (pin 145)
EAR (pin 129)
Table 14. Device ID Register
Version
Part Number (0010 0110 0010 0100)
Manufacturer ID. The 11 bit manufacturer ID
cod for AMD is 00000000001 in accordance
with JEDEC publication 106-A.
Always a logic 1
VDD
....
Figure 50. NAND Tree Circuitry
Am79C972
Am79C972
Core
of RST. The result of the NAND tree test can be ob-
served on the INTA pin. See Figure 50.
Pin 143 (RST) is the first input to the NAND tree. Pin
144 (CLK) is the second input to the NAND tree, fol-
lowed by pin 145 (GNT). All other PCI bus signals fol-
low, counterclockwise, with pin 129 (EAR) being the
last. Table 15 shows the complete list of pins connected
to the NAND tree.
RST must be asserted low to start a NAND tree test se-
quence. Initially, all NAND tree inputs except RST
should be driven high. This will result in a high output
at the INTA pin. If the NAND tree inputs are driven from
high to low in the same order as they are connected to
build the NAND tree, INTA will toggle every time an ad-
ditional input is driven low. INTA will change to low,
when CLK is driven low and all other NAND tree inputs
stay high. INTA will toggle back to high, when GNT is
additionally driven low. The square wave will continue
until all NAND tree inputs are driven low. INTA will be
high, when all NAND tree inputs are driven low. See
Figure 51.
Some of the pins connected to the NAND tree are out-
puts in normal mode of operation. They must not be
driven from an external source until the Am79C972
controller is configured for NAND tree testing.
INTA
A
B
MUX
S
O
INTA (pin 142)
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