AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 68

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

conditions are currently treated as NULL events. Cer-
tain in band non-IEEE 802.3u-compliant flow control
sequences may cause erratic behavior for the
Am79C972 controller. Consult the switch/bridge/router/
hub manual to disable the in-band flow control se-
quences if they are being used.
MII Network Status Interface
The MII also provides signals that are consistent and
necessary for IEEE 802.3 and IEEE 802.3u operation.
These signals are CRS (Carrier Sense) and COL (Col-
lision Sense). Carrier Sense is used to detect non-idle
activity on the network. Collision Sense is used to indi-
cate that simultaneous transmission has occurred in a
half-duplex network.
MII Management Interface
The MII provides a two-wire management interface so
that the Am79C972 controller can control and receive
status from external PHY devices.
The Am79C972 controller can support up to 31 exter-
nal PHYs attached to the MII Management Interface
with software support and only one such device without
software support.
The Network Port Manager copies the PHYAD after the
Am79C972 controller reads the EEPROM and uses it
to communicate with the external PHY. The PHY ad-
dress must be programmed into the EEPROM prior to
starting the Am79C972 controller. This is necessary so
that the internal management controller can work au-
tonomously from the software driver and can always
know where to ac cess the exter nal PHY. The
Am79C972 controller is unique by offering direct hard-
This is followed by a start field (ST) and an operation
field (OP). The operation field (OP) indicates whether
the Am79C972 controller is initiating a read or write op-
eration. This is followed by the external PHY address
(PHYAD) and the register address (REGAD) pro-
grammed in BCR33. The PHY address of 1Fh is re-
served and should not be used. The external PHY may
have a larger address space starting at 10h - 1Fh. This
is the address range set aside by the IEEE as vendor
usable address space and will vary from vendor to ven-
68
1111....1111
Preamble
Bits
32
Bits
ST
01
2
Figure 36. Frame Format at the MII Interface Connection
10 Rd
01 Wr
OP
Bits
2
Address
PHY
Bits
5
Am79C972
ware support of the external PHY device without soft-
ware support. The PHY address of 1Fh is reserved and
should not be used. To access the 31 external PHYs,
the software driver must have knowledge of the exter-
nal PHY’s address when multiple PHYs are present be-
fore attempting to address it.
The MII Management Interface uses the MII Control,
Address, and Data registers (BCR32, 33, 34) to control
an d c om mu ni c at e to th e ex te r n al P H Ys. Th e
Am79C972 controller generates MII management
frames to the external PHY through the MDIO pin syn-
chronous to the rising edge of the Management Data
Clock (MDC) based on a combination of writes and
reads to these registers.
MII Management Frames
MII management frames are automatically generated
by the Am79C972 controller and conform to the MII
clause in the IEEE 802.3u standard.
The start of the frame is a preamble of 32 ones and
guarantees that all of the external PHYs are synchro-
nized on the same interface. (See Figure 36.) Loss of
synchronization is possible due to the hot-plugging ca-
pability of the exposed MII.
The IEEE 802.3 specification allows you to drop the
preamble, if after reading the MII Status Register from
the external PHY you can determine that the external
PHY will support Preamble Suppression (BCR34, bit
6). After having a valid MII Status Register read, the
Am79C972 controller will then drop the creation of the
preamble stream until a reset occurs, receives a read
error, or the external PHY is disconnected.
dor. This field is followed by a bus turnaround field. Dur-
ing a read operation, the bus turnaround field is used to
determine if the external PHY is responding correctly to
the read request or not. The Am79C972 controller will
tri-state the MDIO for both MDC cycles.
During the second cycle, if the external PHY is syn-
chronized to the Am79C972 controller, the external
PHY will drive a 0. If the external PHY does not drive a
0, the Am79C972 controller will signal a MREINT
(CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set
Register
Address
Bits
5
Z0 Rd
10 Wr
Bits
TA
2
Data
Bits
16
Idle
Bit
1
Z
21485C-39