AM79C972BVD\W AMD (ADVANCED MICRO DEVICES), AM79C972BVD\W Datasheet - Page 109

• Manufacturer Part Number: AM79C972BVD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVD\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CSR2: Initialization Block Address 1
Bit
31-16
15-8
Name
RES
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET
or S_RESET, or by setting the
STOP bit.
However, if SSIZE32 is reset
(BCR20,
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as re-
quired for a 32-bit address bus.
Note that the 16-bit software
structures
SSIZE32 = 0 setting will yield
only 24 bits of address for the
Am79C972 bus master access-
es, while the 32-bit hardware for
which the Am79C972 controller is
intended will require 32 bits of ad-
dress.
SSIZE32 = 0, the IADR[31:24]
bits will be appended to the 24-bit
initialization address, to each 24-
bit descriptor base address and
to each beginning 24-bit buffer
address in order to form complete
32-bit addresses. The upper 8
bits that exist in the descriptor ad-
dress registers and the buffer ad-
dress registers which are stored
on board the Am79C972 control-
ler will be overwritten with the
IADR[31:24] value, so that CSR
accesses to these registers will
show the 32-bit address that in-
cludes the appended field.
If SSIZE32 = 1, then software will
provide 32-bit pointer values for
all of the shared software struc-
tures - i.e., descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
Description
Reserved locations. Written as
zeros and read as undefined.
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
Therefore,
bit
specified
8),
then
whenever
by
Am79C972
the
the
7-0
CSR3: Interrupt Masks and Deferral Control
Bit
31-16 RES
15-13 RES
12
11
10
IADR[23:16] Bits 23 through 16 of the address
Name
MISSM
MERRM
RINTM
the upper 8 bits of the initializa-
tion address.
This register is aliased with
CSR17.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
of the Initialization Block. When-
ever this register is written,
CSR17 is updated with CSR2’s
contents.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
zeros and read as undefined.
written as zero.
set, the MISS bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
MISSM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
is set, the MERR bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
MERRM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
is set, the RINT bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RINTM is cleared by H_RESET
Description
Reserved locations. Written as
Reserved locations. Read and
Missed Frame Mask. If MISSM is
Memory Error Mask. If MERRM
Receive Interrupt Mask. If RINTM
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