TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 19

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TS86101G2BCGL

Manufacturer Part Number
TS86101G2BCGL
Description
Manufacturer
E2V
Datasheet

Specifications of TS86101G2BCGL

Lead Free Status / RoHS Status
Not Compliant
Table 4-1.
e2v semiconductors SAS 2009
Symbol
Analog Outputs
OUT_T
OUT_F
Clock Inputs
D_CK_T
D_CK_F
CW_IN_T
CW_IN_F
DSP Clock Outputs
DSP_CK_T
DSP_CK_F
Additional Functions
CS_0, CS_1, CS_2, CS_3
DIODE
GA
Ref
TP
TS86101G2B Pin Description (Continued)
Pin number
T10
T9
A8
A9
T6
T7
R1
P1
R12, T12, R13, T13
T15
P16
R16
A16
Function
In-phase (+) analog output signal
Inverted phase (-) of analog output signal (Vout)
In phase (+) PECL/LVDS Data Ready clock
input signal. The digital data is loaded on the
rising edge of the Data Ready clock signal
Inverted phase (-) of PECL/LVDS Data Ready
clock input signal
In-phase (+) of ECL/PECL/LVDS master clock
input signal. The analog output is sampled and
held on the rising edge of the CW_IN_T signal
Inverted phase (-) of ECL/PECL/LVDS master
clock input signal
In-phase (+) PECL/LVDS DSP clock output
signal. The digital DSP clock
Inverted phase (-) of PECL/LVDS DSP clock
output signal
Selectable shift for DSP output clock (adjust
TDSP)
0 = TTL low or GND
1 = TTL high or left open
Die junction temperature monitoring
Gain adjust (to be connected to the REF pin)
Reference for gain
Non-connected pin
TS86101G2B
0992D–BDC–04/09
19

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