TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 24

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

6.2
24
Power-up Asynchronous Reset/Synchronization of Several TS86101G2B Devices
0992D–BDC–04/09
A power-on asynchronous reset is integrated on the MUXDAC. It is active during the V
to 50% of its final steady-state value – V
To make sure that initialization is effective, the clock should not toggle before V
their final value.
This asynchronous reset allows correct initialization of the divide/4 timing circuitry that drives the 4:1
MUX, therefore providing synchronous DSP output clock signals (DSP_CK_T,DSP_CK_F) and synchro-
nous analog output signals between multiple DACs.
During the power-up reset phase, the applied (CW_IN_T,CW_IN_F) master clock should not toggle.
For initialization, three clock input configurations are authorized:
In all cases, the first pulse width of the master clock should last at least 100 ps and should not toggle in
an undetermined way in order to avoid metastability of the clock.
For DSP systems that require several MUXDACs to be synchronized, the following design and protocol
rules apply:
• Differential clock input: the master clock can start indifferently at a logical high or low.
• Single-ended clock input on CW_IN_T: the master clock must be at a logical high during reset and
• Single-ended clock input on CW_IN_F: the master clock must be at a logical low during reset and
1. The MUXDACs must be powered-up under DSP executive control, with their clocks kept inac-
2. A delay equalling the settling time of the power supplies (time until they reach at least 90% of
3. The MUXDAC clocks can then be commanded to their active state. In order to reduce the prob-
4. All MUXDAC clock paths within a given DSP should be designed according to the standard
start with a falling edge.
start with a rising edge.
tive. If used in differential mode (recommended), the clocks should be previously set to either a
high or low state, and in any case the clocks should not be toggling.
their steady state) must be respected before proceeding to step 3.
ability of clock meta-stability, the first pulse should last at least 100 ps and should not toggle in
an undetermined way.
high-speed design rules.
EEA
/V
EED
<–2.5V).
e2v semiconductors SAS 2009
EED
TS86101G2B
/V
EEA
EED
exceed 90% of
ramp-up, (up