TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 8

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

2.2
Table 2-4.
Notes:
8
Parameter
Data and data ready maximum allowable input jitter
Input data rise/fall time
Data ready rise/fall time
Tsetup
Thold
Input data rate (ports A, B, C and D)
Input data pulse width (ports A, B, C and D)
CW_IN clock input frequency
CW_IN master clock input jitter
CW_IN to DSP clock output delay with clock shift 0000
CW_IN to DSP clock output delay with clock shift 1111
DSP clock output phase tuning range
DSP clock output phase tuning steps
Data ready to CW_IN clock timing:
Forbidden area
Pipeline delay
TOD
TPD
Analog output rise/fall time
(5)(6)
(5)
(2)
(2)
see
Timing Characteristics
1. Digital input data rise/fall time: defined between 20% to 80%.
2. Exclusive of period (pp) jitter on both Data and on Data Ready.
3. CW_IN clock input jitter over 5 GHz bandwidth. MUXDAC also operates with CW_IN clock showing more jitter but this may
4. Guaranteed by design.
5. See
6. TPD can be directly measured at package input/output, between CW_IN clock and analog output.
7. Full-scale analog output (10% to 90%).
(propagation delay)
see
0992D–BDC–04/09
Figure 5-2 on page 21
degrade performance (SNR and NPR).
Figure 5-2 on page 21
(4)
Timing Characteristics: 50Ω // 2pF Loading Conditions on Each Single-ended Output. Absolute Timing
Values are Given at Package Input/Output Balls
“Definitions of Terms” on page
(1)
(1)
(7)
(3)
(Figure 5-4 on page
35.
22)
Level
Test
4
4
4
4
4
4
4
4
4
4
1
1
4
4
(at 350 MWord/s)
–1.3 ns
2.5 ns
5.7 ns
Min
2.1 ns + 1 clock cycle
5.2 ns + 1 clock cycle
Pipeline delay + TOD
1 clock cycle
0 to 3.1 ns
200 ps
180 ps
3.7 ns
Typ
e2v semiconductors SAS 2009
TS86101G2B
300 ps peak- to-
350 MWords/s
1400 MHz
1 ps rms
500 ps
500 ps
600 ps
Max
peak