TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 29

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

8. Timing Diagram
Figure 8-1.
e2v semiconductors SAS 2009
(DSP_CK_T, DSP_CK_F)
(CW_IN_T, CW_IN_F)
(D_CK_T, D_CK_F)
2nd Master Latches
3rd Master Latches
1st Master Latches
4 -> 1 MUX Output
2nd Slave Latches
3rd MS DAC Bank
Datas In
3rd Slave Latches
Port C and Port D
1st Slave Latches
Port C and Port D
Port C and Port D
Port C and Port D
Port A and Port B
Port A and Port B
CW Master Clock
Port A and Port B
Port A and Port B
Data Ready
2 VPP Differential on 100Ω
DAC Bank
DAC Bank
DSP Out
1 Vpp Single on 50Ω
(OUT_T, OUT_F)
Port A
Port B
Port C
Port D
Clock
Analog Output
Simplified Timing Diagram
Note:
Data Skew
Jitter = 300 ps p.p. max
F = 1.2 GHz
0
All timing parameters are defined under
Data N - 8
TDSP
TOD Includes Internal Propagation Delay: (Phi4, Tconv and Package Propagation Delay)
Tsetup
Data N - 7
Propagation Delay TPD = Pipeline Delay + TOD = 1 Clock Cycle + TOD
Jitter = 300 ps p.p. max
Clock Shift
0000
Data N - 6
TCW
(15 steps of 200 ps)
Clock Shift Range:
200 ps to 3.1 ns
Thold
Data N - 5
Data N - 4
0000
0000
Phi 4
Phi 4
Shift Range: 3.1 ns
1111
Data N - 3
TPD
Data N - 2
Tconv 1 Clock Cycle
0000
1111
1111
Shift Range: 3.1 ns
Data N -1
“Definitions of Terms” on page
Data N
1111
0
Full-scale
Data N + 1
Step
Data N + 2
Data N + 3
Clock
%4
Shift
35.
4
4 x 10
Shift Select
DSP Clock Out
Data Ready
Data In
TS86101G2B
0992D–BDC–04/09
D S P
29