TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 23

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

5.3.1
5.3.2
6. Main Features of the TS86101G2B
6.1
e2v semiconductors SAS 2009
Input MUX
Tuning the DSP Clock Output Phase
Analog Output Data Switching Information
Case 1:
If the D_CK clock edge occurs before the forbidden zone, data N will be transferred internally from the
first to the second bank of latch (see
Case 2:
If the D_CK clock edge occurs after the forbidden zone, data N +1 will be transferred internally from the
first to the second bank of latch (see
The DSP clock output phase may be tuned over a range of 3.1 ns in 15 discrete steps of 200 ps each,
plus a propagation delay of 2.1 ns (the 2.10 ns value is an absolute timing value measured from CW_IN
input ball to DSP Clock output ball), by correctly setting the 4-bit address input CS_0, CS_1, CS_2 and
CS_3 from 0000 to 1111:
The analog output data changes on the CW_IN master clock’s rising edge, after one clock cycle pipeline
delay, plus TOD (output propagation delay). TOD includes the following:
The typical value of TOD is 3.7 ns, assuming a 50Ω // 2 pF load.
The 4:1 integrated input MUX of the TS86101G2B provides the user with the capacity to apply an input
data rate four times lower than the effective sampling frequency used:
Data rate = Fs/4 = F(DSP_CK) = F(D_CK)
Where:
Since this input MUX is not programmable, all four ports must be used for proper operation of the DAC.
• Propagation time delays of the packaging accesses
• The DAC’s core internal conversion time and other internal propagation delays
– 0000: 2.1 ns + 0
– 0001: 2.1 ns + 200 ps
– …
– 1111: 2.1 ns + 3.1 ns
– F(DSP_CK) is the frequency of the DSP output clock
– F(D_CK) is the frequency of the Data Ready input clock
Figure 8-2 on page
Figure 8-2 on page
30).
30).
TS86101G2B
0992D–BDC–04/09
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