TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 40

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TS86101G2BCGL

Manufacturer Part Number
TS86101G2BCGL
Description
Manufacturer
E2V
Datasheet

Specifications of TS86101G2BCGL

Lead Free Status / RoHS Status
Not Compliant
40
0992D–BDC–04/09
Figure 12-6. LVDS
Figure 12-7. Single-ended Implementation of DATA_IN and Data Ready Inputs
The TS86101G2B MUXDAC digital input and Data Ready input signals provide PECL and LVDS level
formats in differential mode. When used in single-ended mode, the associated false signal must be tied
to the common mode voltage of the true signal, as shown in
VOH = 1.4V
VOL = 1.1V
LVDS
Driver
DATA_IN_T or D_CK_T
Common Mode Voltage
Package Pins
Z = 50Ω
Z = 50Ω
MUXDAC
50Ω Lines
Figure
12-7.
DGND
Data Input/Data Ready Input
50Ω
e2v semiconductors SAS 2009
10 pF
TS86101G2B
MUXDAC
50Ω
GND
10 pF
50Ω

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