W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 114

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.2.6 Configuration Register 5 (CR5), default = 00H
When the device is in Extended Function mode and EFIR is 05H, the CR5 register can be accessed
through EFDR. The bit definitions are as follows:
Bit 7- bit 4: Reserved
ECPFTHR3-0 (bit 3-0): These four bits define the FIFO threshold for the ECP mode parallel port. The
11.2.7 Configuration Register 6 (CR6), default = 00H
When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed
through EFDR. The bit definitions are as follows:
Bit 7- bit 6: Reserved
SEL4FDD (Bit 5): Selects four FDD mode
0
1
select four drives.
Selects two FDD mode (default, see Table 8-2)
Selects four FDD mode
DSA , DSB , MOA and MOB output pins are encoded as show in Table 8-3 to
default value is 0000 after power-up.
7
7
0
6
6
5
5
4
4
3
3
2
2
- 107 -
1
1
W83877ATF/W83877ATG
0
reserved
FDCTRI
reserved
FDCPWD
FIPURDWM
SEL4FDD
reserved
reserved
Publication Release Date:November 2006
ECPFTHR0
ECPFTHR1
ECPFTHR2
reserved
reserved
reserved
reserved
ECPFTHR3
Version 1.0