W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 58

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 1:
Bit 0:
(2) UART FIFO Control Register (UFR):
Legacy UART: The definition of this register is same as Legacy UART mode.
Advanced UART:
Bit 7, 6:
Bit 5, 4:
Advanced
Reset Value
Legacy
MODE
UART
UART
RXFTL1, 0
(Bit 7, 6)
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Clear to 0 when this
register is read.
RXTH_I - Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal to or larger than the
threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and
below the threshold level. Clear to 0 when RBR is less than threshold level from reading
RBR.
RXFTL1, 0 - Receiver FIFO Threshold Level
Definition is same as Legacy UART, that is to determine the RXTH_I to become 1 when
the Receiver FIFO Threshold Level is equal or larger than the defined value shownbelow.
Note that the FIFO Size is referred to SET2.Reg4.
TXFTL1, 0 - Transmitter FIFO Threshold Level
To determine the TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the
Transmitter Threshold Level is less than the programmed value shown as follows.
RXFTL1
RXFTL1
00
01
10
11
(MSB)
(MSB)
BIT 7
0
RXFTL0
RXFTL0
(LSB)
(LSB)
BIT 6
0
RX FIFO Threshold Level
TXFTL1
(MSB)
BIT 5
( FIFO Size: 16-byte)
0
0
14
TXFTL0
1
4
8
(LSB)
BIT 4
0
0
- 51 -
W83877ATF/W83877ATG
BIT 3
0
0
0
Publication Release Date:November 2006
TXF_RST RXF_RST EN_FIFO
TXF_RST RXF_RST EN_FIFO
RX FIFO Threshold Level
BIT 2
0
( FIFO Size: 32-byte)
BIT 1
16
26
1
4
0
Version 1.0
BIT 0
0