W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 160

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.4 ACPI Registers (ACPIRs)
The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A
register block may be a event register block which deals with ACPI events, or a control register block
which deals with control features. The ordering in the event register block is the status register,
followed by the enable register.
Each event register, if implemented, contains two egisters: a status register and an enable register,
both in 16-bit size. The status register indicates what defined function needs the ACPI System Control
Interrupt (SCI). When the hardware event occurs, the defined status bit is set. However, to generate
the SCI, the associated enable bit must be set. If the enable bit is not set, the software can examine
the state of the hardware event by reading the status bit without generating an SCI interrupt.
Any status bit, unless otherwise noted, can only be set by some defined hardware event. It is cleared
by writing a 1 to its bit position; writing a 0 has no effect. Except forsome special status bits, every
status bit has an assiciated enable bit in the same bit position in the enable register. Those status bits
which have no respective enable bit are read for special purposes. Reserved or un-implemented
enable bits always return zero, and writing to these bits should have no effect.
The control bit in the control register provides some special control functions over the hardware event,
or some special control over SCI event. Reserved or un-implemented control bits always return zero,
and writing to those bits should have no effect.
Table 8-4 lists the PM1 register block and the relative locations of the registers within it. The base
address of PM1 register block is named as PM1a_EVT_BLK in the ACPI specification. The base
address should range from 01,0000,0000
of PM1 register block should be set to 0 and the base address is in the 16-byte alignment.
Table 8-5 lists the GPE register block and the relative locations within it. The base address of power
management event block GPE is named as GPE0_BLK in the ACPI specification. The base address
should range from 01,0000,0000
address should be set to 0 and the base address is in the 8-byte alignment.
11.4.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
Default Value:
Attribute:
Size:
<CR33> System I/O Space
00h
Read/write
8 bits
7
6
b
to 11,1111,1000
5
b
4
to 11,1111,0000
3
- 153 -
b
2
,i.e., 100H ~ 3F8H, where bit 0 of the base
W83877ATF/W83877ATG
1
b
,i.e., 100H ~ 3F0H, where bit 1 and bit 0
0
Publication Release Date:November 2006
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
Version 1.0