W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 99

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 2: Read/Write
Bit 1: Read only
Bit 0: Read only
7.3.11 Bit Map of ECP Port Registers
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
ecpDFifo
ecpAFifo
cnfgA
cnfgB
cFifo
data
tFifo
dsr
dcr
ecr
1
0
0
1
0
1
Addr/RLE
compress
nBusy
PD7
D7
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1:
During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0:
This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the
FIFO.
(c) dmaEn = 0 direction = 1:
This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be
read from the FIFO.
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
The FIFO contains at least 1 byte of data.
The FIFO is completely empty.
1
0
intrValue
MODE
PD6
nAck
D6
1
0
Directio
PError
PD5
D5
0
1
Parallel Port Data FIFO
nErrIntrEn
ECP Data FIFO
ackIntEn
Select
PD4
Test FIFO
- 92 -
D4
1
1
Address or RLE field
W83877ATF/W83877ATG
SelectIn
dmaEn
nFault
PD3
D3
0
1
serviceIntr
PD2
nInit
D2
1
0
1
autofd
PD1
D1
full
1
0
1
strobe
empty
PD0
D0
1
0
1
NOTE
2
1
1
2
2
2