W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 146

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

URAPME (Bit 1): UART A power management enable.
.
URBPME (Bit 0): UART B power management enable.
11.2.41
When the device is in Extended Function mode and EFIR is 33H, the CR33 register can be accessed
through EFDR. The bit definitions are as follows:
PM1AD7 - PM1AD2 (Bit 7 - bit 2): Base address of the power management register block PM1.
This address is the base address of PM1a_EVT_BLK in the ACPI specification. The based address
should range from 01,0000,0000
base address should be set to 0 and the based address is in the 16-byte alignment. Note that the
based address of PM1a_CNT_BLK is equal to PM1a_EVT_BLK + 4, and PM_TMR_BLK is equal to
PM1a_EVT_BLK + 8.
Bit 1 - bit 0: Reserved, fixed at 0.
11.2.42
When the device is in Extended Function mode and EFIR is 34H, the CR34 register can be accessed
through EFDR. The bit definitions are as follows:
0
1
0
1
Configuration Register 33 (CR33), default=00H
Configuration Register 34 (CR34), default=00H
disable and the auto power management function.
enable auto power management function, if this bit and CHIPPME(CR32 bit 7) are both
set to 1.
disable the auto power management functions.
enable the auto power management function, if this bit and CHIPPME(CR32 bit 7) are
both set to 1.
7
7
6
6
b
to 11,1111,0000
5
5
4
4
3
3
- 139 -
b
,i.e., 100H ~ 3F0H, where bit 1 and bit 0 of the
2
2
W83877ATF/W83877ATG
1
1
0
0
Publication Release Date:November 2006
reserved
reserved
PM1AD2
PM1AD3
PM1AD4
PM1AD5
PM1AD6
PM1AD7
reserved
GPEAD1
GPEAD2
GPEAD3
GPEAD4
GPEAD5
GPEAD6
GPEAD7
Version 1.0