W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 43

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DSKCHG (Bit 7):
This bit indicates the status of DSKCHG input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
5.2.9
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
Configuration Control Register (CC Register) (Write base address + 7)
x
7
X
7
x
6
X
6
x
5
X
5
X
x
4
4
X: Reserved
X
3
- 36 -
x
3
X
2
:
x
2
Reserved
W83877ATF/W83877ATG
1
1
0
0
DRATE0
DRATE1
NOPREC
DRATE0
DRATE1