W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 141

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 4 :APEDCRC - Append CRC to receiver when a frame is end.
Bit 3 :ENBNKSEL - Bank select enable
Bit 2 :CLKINSEL - Clock input selection
Bit 1, Bit 0: Reserved
11.2.37
When the device is in Extended Function mode and EFIR is 2D
through EFDR. This register default value is 00
This register controls the data rate selection for FDC. It also controls if precompensation is enabled.
DRTA1, DRTA0 (bit 1 - bit 0):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD A as follows:
Configuration Registers (CR2D)
= 0 No append hardware CRC value as data in FIR/MIR mode
= 1 Append hardware CRC value as data in FIR/MIR mode
= 0 Disable UART B bank selection
= 1 Enable UART B bank selection
= 0 The clock on pin CLKIN is 24 MHz
= 1 The clock on pin CLKIN is 48MHz
7
6
5
4
3
16
- 134 -
. The bit definitions are as follows:
2
1
W83877ATF/W83877ATG
0
16
DRTA0
DRTA1
DIS_PRECOMP0
DRTB0
DRTB1
DIS_PRECOMP1
Reserved
Reserved
, the CR2D register can be accessed