W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 12

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4. PIN DESCRIPTION
Note: Refer to section 9.2 DC CHARACTERISTICS for details.
I/O
I/O
I/O
I/O
OUT
OUT
OD
OD
IN
IN
IN
4.1
D0−D7
A0−A10
IOCHRDY
MR
A11
AEN
DRQ_A
DRQ_B
IOR
IOW
DACK_ A
DACK_B
CS
t
ts
cs
8tc
12t
12ts
24t
12
24
SYMBOL
8t
12t
- TTL level input pin
- TTL level Schmitt-triggered input pin
- CMOS level Schmitt-triggered input pin
Host Interface
- TTL level output pin with 8 mA source-sink capability; CMOS level input voltage
- TTL level bi-directional pin with 12 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability and Schmitt-triggered input
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 8 mA source-sink capability
- TTL level output pin with 12 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
66-73
51-55
57-61
100
PIN
75
62
63
64
41
39
98
5
6
2
OUT
OUT
I/O
OD
IN
IN
IN
IN
IN
IN
IN
I/O
IN
IN
24t
ts
ts
ts
ts
ts
ts
ts
t
24
t
12t
8t
System data bus bits 0-7.
System address bus bits 0-10.
In EPP Mode, this pin is the I/O Channel Ready output to extend
the host read/write cycle.
Master Reset. Active high. MR is low during normal operations.
Active low chip select signal.
System address bus bit 11, when 16-bit address decoder is set
to logic 0 in which CR16.bit6 ( EN SA
System address bus enable.
CPU I/O read signal.
CPU I/O write signal.
DMA acknowledge signal A.
DMA request signal A.
DMA request signal B.
DMA acknowledge signal B.
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W83877ATF/W83877ATG
FUNCTION
Publication Release Date:November 2006
16
).
Version 1.0