FDC37M817-MS Standard Microsystems (SMSC), FDC37M817-MS Datasheet - Page 121

• Manufacturer Part Number: FDC37M817-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M817-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Keyboard Data Write
This is an 8 bit write only register. When written,
the C/D status bit of the status register is cleared
to zero and the IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by
"ENABLE FLAGS", when read, the KIRQ output is
cleared and the OBF flag in the status register is
cleared.
AUXOBF1 must be cleared in software.
Host-to-CPU Communication
The host system can send both commands and
data to the Input Data register.
differentiates between commands and data by
reading the value of Bit 3 of the Status register.
When bit 3 is "1", the CPU interprets the register
contents as a command. When bit 3 is "0", the
CPU interprets the register contents as data.
During a host write operation, bit 3 is set to "1" if
SA2 = 1 or reset to "0" if SA2 = 0.
KIRQ
If "EN FLAGS" has been executed and P24 is set
to a one: the OBF flag is gated onto KIRQ. The
KIRQ signal can be connected to system interrupt
to signify that the FDC37M81x CPU has written to
the output data register via "OUT DBB,A". If P24
is set to a zero, KIRQ is forced low. On power-up,
after a valid RST pulse has been delivered to the
device, KIRQ is reset to 0. KIRQ will normally
reflects the status of writes "DBB".
normally selected as IRQ1 for keyboard support.)
If "EN FLAGS” has not been executed: KIRQ can
be controlled by writing to P24. Writing a zero to
P24 forces KIRQ low; a high forces KIRQ high.
OUT DBB
8042 INSTRUCTION
If not enabled, the KIRQ and/or
Set OBF, and, if enabled, the KIRQ output signal goes high
Table 48 - Host Interface Flags
The CPU
(KIRQ is
121
Keyboard Command Write
This is an 8 bit write only register. When written,
the C/D status bit of the status register is set to
one and the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the
description of the Status Register for more
information.
CPU-to-Host Communication
The FDC37M81x CPU can write to the Output
Data register via register DBB. A write to this
register automatically sets Bit 0 (OBF) in the
Status register. See Table 48.
MIRQ
If "EN FLAGS" has been executed and P25 is set
to a one:; IBF is inverted and gated onto MIRQ.
The MIRQ signal can be connected to system
interrupt to signify that the FDC37M81x CPU has
read the DBB register.
If "EN FLAGS” has not been executed, MIRQ is
controlled by P25, Writing a zero to P25 forces
MIRQ low, a high forces MIRQ high. (MIRQ is
normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software
controlled Gate A20 or user defined output.
EXTERNAL
INTERFACE
Industry-standard PC-AT-compatible keyboards
employ a two-wire, bidirectional TTL interface for
data transmission. Several sources also supply
FLAG
KEYBOARD
AND
MOUSE