FDC37M817-MS Standard Microsystems (SMSC), FDC37M817-MS Datasheet - Page 40
FDC37M817-MS
Manufacturer Part Number
FDC37M817-MS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.FDC37M817-MS.pdf
(198 pages)
Specifications of FDC37M817-MS
Pin Count
100
Lead Free Status / RoHS Status
Compliant
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PCN
POLL
PRETRK
R
RCN
SC
SK
SRT
ST0
ST1
ST2
ST3
WGATE
SYMBOL
Present
Cylinder
Number
Polling Disable
Precompensati
on Start Track
Number
Sector Address The sector number to be read or written. In multi-sector transfers, this
Relative
Cylinder
Number
Number of
Sectors Per
Track
Skip Flag
Step Rate
Interval
Status 0
Status 1
Status 2
Status 3
Write Gate
NAME
Table 17 - Description of Command Symbols
The current position of the head at the completion of Sense Interrupt
Status command.
When set, the internal polling routine is disabled. When clear, polling is
enabled.
Programmable from track 00 to FFH.
parameter specifies the sector number of the first sector to be read or
written.
Relative cylinder offset from present cylinder as used by the Relative
Seek command.
The number of sectors per track to be initialized by the Format
command. The number of sectors per track to be verified during a
Verify command when EC is set.
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If Read
Deleted is executed, only sectors with a deleted address mark will be
accessed. When set to "0", the sector is read or written the same as
the read and write commands.
The time interval between step pulses issued by the FDC.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the
1 Mbit data rate. Refer to the SPECIFY command for actual delays.
Registers within the FDC which store status information after a
command has been executed. This status information is available to
the host during the result phase after command execution.
Alters timing of WE to allow for pre-erase loads in perpendicular drives.
40
DESCRIPTION
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