FDC37M817-MS Standard Microsystems (SMSC), FDC37M817-MS Datasheet - Page 145

• Manufacturer Part Number: FDC37M817-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M817-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical
Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 4: The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is
LOGICAL
NUMBER
DEVICE
0x00
0x01
0x02
0x03
0x04
0x05
Device I/O map, then read or write is not valid and is ignored.
0x04.
Serial Port
Serial Port
LOGICAL
Reserved
Reserved
DEVICE
Parallel
FDC
Port
Table 55 - I/O Base Address Configuration Register Description
1
2
REGISTER
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
INDEX
n/a
n/a
the base address is on an 8-
ON 8 BYTE BOUNDARIES
ON 4 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
EPP is only available when
(all modes supported,
(EPP Not supported)
[0x100:0x0FFC]
[0x100:0x0FF8]
[0x100:0x0FF8]
[0x100:0x0FF8]
[0x100:0x0FF8]
byte boundary)
145
BASE I/O
(NOTE 1)
RANGE
n/a
n/a
or
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TDR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
n/a
n/a
+0 : Data|ecpAfifo
+1 : Status
+2 : Control
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+400h : cfifo|ecpDfifo|tfifo |cnfgA
+401h : cnfgB
+402h : ecr
+0 : RB/TB|LSB div
+1 : IER|MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LCR
+6 : MSR
+7 : SCR
+0 : RB/TB|LSB div
+1 : IER|MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LCR
+6 : MSR
+7 : SCR
BASE OFFSETS
FIXED