PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 106

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
halfres mode, the resulting captured planar data is as
shown in
WIDTH/4 chrominance samples are captured. In this
mode, START_X and WIDTH must be a multiple of four.
Horizontal-resolution reduction is performed as shown in
Figure 6-13
ventions of the pixels in memory depends on the SC
(sampling convention) bit in the VI_CTL register. Assum-
ing that the camera sampling positions obey the conven-
tions shown in
are supported in memory:
• If SC=0, co-sited luminance and chrominance sam-
• If SC=1, interspersed chrominance samples result,
The filtering process applies mirroring at the edge of the
active video area, as per
For both filters, computed video data is clamped to 01h if
result of the filter is less than 01h and clamped to FFh if
greater than FFh.
6-10
Figure 6-15. Raw and message passing modes view of VI MMIO registers.
ples result as shown in
sponds to the standard YUV 4:2:2 sampling
conventions.
as shown in
subsampling of the chroma components) identical to
the MPEG-1 sampling conventions. If vertical sub-
sampling is desired, it can either be performed in
software on the DSPCPU or in hardware by the ICP.
MMIO_BASE
0x10 141C
0x10 1400
0x10 1404
0x10 1408
0x10 1414
0x10 1418
offset:
Figure
or
Figure
Figure
6-12. Note that WIDTH/2 luminance and
Figure
VI_STATUS (r)
VI_CTL (r/w)
VI_CLOCK (r/w)
VI_BASE1 (r/w)
VI_BASE2 (r/w)
VI_SIZE (r/w)
PRELIMINARY SPECIFICATION
6-14. The spatial sampling con-
6-5, two possible spatial formats
6-14. This form is (after vertical
Figure
Figure
6-7.
Highway bandwidth error ACK
6-13. This corre-
31
31
software RESET
SELFCLOCK
DIAGMODE
Little endian
RESERVED
27
27
Highway bandwidth error
SLEEPLESS
23
Capture enable
23
INT enable
6.5
All raw capture modes (raw8, raw10s and raw10u) be-
have similarly. VI_DATA information is captured at the
rate of the sender’s clock, without any interpretation or
start/stop of capture on the basis of the data values. Any
clock cycle in which VI_DVALID is asserted leads to the
capture of one data sample. Samples are 8 or 10 bits
long (raw8 versus raw10 modes). For the 8-bit capture
mode, four samples are packed to a word. For the 10-bit
capture modes, two 16-bit samples are packed to a
word. The extension from 10 to 16 bits uses sign exten-
sion (raw10s) or zero extension (raw10u).
For 8-bit and 16-bit capture, successive captured values
are written to increasing memory addresses. For 16-bit
capture, the byte order with which the 16-bit data is writ-
ten to memory is governed by the LITTLE ENDIAN bit.
The VI LITTLE ENDIAN bit should be set the same as the
DSPCPU endianness (PCSW.BSX). This ensures that
the DSPCPU sees correct 16-bit data.
Figure 6-15
MMIO registers.
associated with raw-mode capture. The initial state is
reached on software or hardware reset as described in
Section 6.1.4, “Hardware and Software
set, all status and control bits are set to ‘0’. In particular,
CAPTURE_ENABLE is set to ‘0’ and no capture takes
place.
Once the software has programmed BASE1 and BASE2
(with the start addresses of two SDRAM buffer areas
SIZE (in samples)
21
Highway bandwidth error
BASE1
BASE2
19
19
RAW CAPTURE MODES
VALID
OVERRUN
BUF2FULL
illustrates the ‘raw-mode’ view of the VI
Interrupt enables
15
15
Figure 6-16
DIVIDER
(message mode only)
11
MODE
Philips Semiconductors
shows the major VI states
OVR
BUF2FULL
BUF1ACTIVE
BUF1FULL
OVERFLOW
OVF
BUF1FULL
ACK_OVR
7
ACK_OVF
Reset”. Upon re-
0
0
0
0
0
0
ACK2
0
0
0
3
ACK1
0
0
0
0
0
0
0
0
0
0
1
)