PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 47

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
1.9.7.16
Notes: 1. See the timing measurement conditions in
1.9.7.17
Notes: 1. See the timing measurement conditions in
1.9.7.18
Notes: 1. Interrupt latency limits SSI to a practical use at a bit rate of 1.5 Mbit/sec.
f
T
T
T
f
T
T
T
T
T
f
T
T
T
AI-SCK
AO-SCK
SSI-CLK
su-SCK
su-SCK
su-CLK
h-SCK
SCK-WS
SCK-DV
SCK-DV
h-SCK
SCK-WS
CLK-DV
h-CLK
Symbol
Symbol
Symbol
2. The timing measurements are done with respect to the clock edge according to CLOCK_EDGE
3. SER_MASTER asserted, i.e. Audio In is the source of AI_WS. See the timing measurement condition in
2. See the timing measurement conditions in
3. The timing measurements are done with respect to the AO_SCK clock edge according to CLOCK_EDGE
4. PNX1300/01/02/11 is the serial interface master, i.e. AO_SCK, AO_WS are outputs
5. PNX1300/01/02/11 is serial interface slave, i.e. AO_SCK, AO_WS are inputs
6. See the timing measurement conditions in
2. See the timing measurement conditions in
3. See the timing measurement conditions in
AudioIn I/O timing
Audio Out I/O timing
SSI I/O timing
Audio In AI_SCK clock frequency
Input setup time to AI_SCK
Input hold time from AI_SCK
AI_SCK to AI_WS
Audio Out AO_SCK clock frequency
AO_SCK to AO_SDx valid
AO_SCK to AO_SDx valid
Input setup time to AO_SCK
Input hold time from AO_SCK
AO_SCK to AO_WS
SSI_CLK clock frequency
SSI_CLK to data valid
Input setup time to SSI_CLK
Input hold time from SSI_CLK
Parameter
Parameter
Parameter
Figure
Figure
Figure
Figure
Figure
Figure
1-19.
1-21.
1-23.
1-22.
1-24.
1-25.
PRELIMINARY SPECIFICATION
Min.
Min.
Min.
3
2
2
2
4
2
2
3
2
Max
Max
Max
22
10
22
12
12
10
20
12
Units
Units
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
Notes
1,3,4
1,3,5
2,3,5
2,3,5
3,4,6
1,2
1,2
Figure
3
1
2
3
3
1-20.
Pin List
1-21