PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 150

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
9.6.2
Refer to
MMIO registers should be set to transmit 16 or 32 bits of
stereo data via an I
converter with a 64-bit serial frame.
Table 9-8. Example setup for 64-bit I
9.7
In addition to the left and right data fields that are gener-
ated based on autonomous DMA action, a serial frame
generated by the AO unit can be set to contain 1 or 2
control fields up to 16 bits in length. Each control field can
be independently enabled/disabled by the CC1_EN,
CC2_EN bits in AO_CTL. The content shifted into the
frame is taken from the CC1 and CC2 field in the AO_CC
register. The CC1_POS and CC2_POS fields in the
AO_CFC register determine the first bit position in the
frame where the control field is emitted. The field is emit-
ted observing the setting of DATAMODE, i.e. LSB or
MSB first.
The CC_BUSY bit in AO_STATUS indicates if the AO
unit is ready to receive another CC1, CC2 value pair.
Writing a new value pair to AO_CC writes the value into
a buffer register, and raises the CC_BUSY status. As
soon as both CC1 and CC2 values have been copied to
a shadow register in preparation for transmission,
CC_BUSY is negated, indicating that the AO logic is
ready to accept a new codec control pair. The old CC1/
9-6
Figure 9-3. Serial frame (64 bits) of a 18-bit precision I
POLARITY
LEFTPOS
RIGHTPOS
DATAMODE
SSPOS
CLOCK_EDGE
WSDIV
WS_PULSE
AO_SCK
AO_WS
AO_SDx
Field
CODEC CONTROL
Figure 9-3
I
2
S Serial Framing Example
Value
0
32
63
0
0
0
0
0
0
and
1
2
S serial standard to an 18-bit D/A
left channel data
PRELIMINARY SPECIFICATION
2
Table 9-8
Frame starts with negedge AO_WS.
LEFT[msb] will go to serial frame
position 0.
RIGHT[msb] will go to serial frame
position 32.
MSB first.
Stop with LEFT/RIGHT[0], send 0’s
after.
(for 32 bits/sample mode, this field
could be set to 14 to ensure zeroes
in all unused bit positions)
AO_SDx change on negedge
AO_SCK
Serial frame length = 64.
emit 50% duty cycle AO_WS.
3
to see how the AO unit
Explanation
n
(18)
17
2
S framing
18
30
31
32
33
right channel data
2
S D/A converter.
Table 9-9. AO MMIO codec control/status fields
CC2 data keeps being transmitted - i.e. software is not
required to provide new CC1 and CC2 data.
Software always needs to ensure that the CC_BUSY sta-
tus is negated before writing a new CC1, CC2 pair. By
polling CC_BUSY, the DSPCPU can emit a sequence of
individual audio frames with distinct control field values
reliably. This can, for example, be used during codec ini-
tialization. No provision is made for interrupt driven oper-
ation of such a sequence of control values; it is assumed
that after initialization, the value of control fields deter-
mine slow, asynchronous changing parameters such as
volume.
It is legal to program the control field positions within the
frame such that CC1 and CC2 overlap each other and/or
left/right data fields. If two fields are defined to start at the
same bit position, the priority is left (highest), right, CC1
then CC2. The field with the highest priority will be emit-
ted starting at the conflicting bit position. If a field f2 is de-
fined to start at a bit position i that falls within a field f1
starting at a lower bit position, f2 will be emitted starting
from i and the rest of f1 will be lost. Any bit positions not
belonging to a data or control field will be emitted as ‘0’.
CC1 (16)
CC1_POS
CC1_EN
CC2(16)
CC2_POS
CC2_EN
CC_BUSY
Field Name
n
(18)
49
50
The 16-bit value of CC1 is shifted into each
emitted serial frame starting at bit position
CC1_POS, as long as CC1_EN is asserted.
Defines the bit position within a serial frame
where the first data bit of CC1 is placed.
RESET Default 0.
0 ⇒ CC1 emission disabled (RESET default)
1 ⇒ CC1 emission enabled.
The 16-bit value of CC2 is shifted into each
emitted serial frame starting at bit position
CC2_POS, as long as CC2_EN is asserted.
Defines the bit position within a serial frame
where the first data bit of CC2 is placed.
Default 0.
0 ⇒ CC2 emission disabled (RESET default)
1 ⇒ CC2 emission enabled.
0 ⇒ AO is ready to receive a CC1, CC2 pair
1 ⇒ AO is not ready to receive a CC1, CC2
51
52
(RESET default).
pair. Try again in a few SCK clock inter-
vals.
Philips Semiconductors
62
63
Description
0
1
left channel data
n+1
(18)