PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 249

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
16.4.3
The I
garding the transfer in progress and the nature of inter-
rupts associated with
Table 16-3. IIC_SR register
The IIC_SR register is read only and is intended as the
primary source of status regarding current
The IIC_SR register must be used in conjunction with the
IIC_CR register. The interrupt sources of the IIC_SR reg-
ister are individually enabled by writing to the appropriate
enable bit in the IIC_CR register. The bitfield definitions
of the IIC_SR register are presented in
IIC_SR provides four sources of interrupts. Note: the in-
terrupt should be set up as level triggered interrupt.
• GDI interrupt — The GDI bit together with the FI bits
• FI interrupt — See GDI bit definition and GDI/FI
• SANACKI interrupt — This interrupt flag bit indicates
25:23
Bits
15:8
7:0
31
30
29
28
27
26
22
21
provide status about I
interpretation of GDI/FI bit combinations are different
depending on whether the I
transmit or master receive mode. Refer to
and
transmit and receive definitions in
Table
that a slave address was transmitted but no slave on
2
C
Table 16-6
DIRECTION Direction of current data transfer.
status register contains status information re-
Field Name
16-6.
SDA_STAT
SCL_STAT
SANACKI
SDNACKI
Reserved
Reserved
IIC_SR Register
STATE
RBC
GDI
FI
for GDI/FI interpretation.
Good Data Interrupt. This is the nor-
mal transfer complete interrupt flag.
This interrupt may be asserted without
the IIC_SR.FI interrupt bit at the end of
an I
an I
Full Interrupt. This interrupt indicates
the condition of the IIC_DR register
dependent upon whether the I
face is in receive or transmit mode.
Slave Address No Acknowledge Inter-
rupt.
Slave Data No Acknowledge Interrupt.
This bit is used to examine the state of
the external I
polarity is:
1 = SDA pad is low
0 = SDA pad floated high
This bit is used to examine the state of
the external I
polarity is:
1 = SCL pad is low
0 = SCL pad floated high
The STATE field indicates the micro-
activity of the I
Read as ‘0’
Remaining Byte Count.
Read as ‘0’
I
2
C
2
2
operation.
C transfer or after master abort of
C transfer.
2
C transfer completion. The
2
C interface is in master
2
2
Definition
C SDA data pin. Bit
C SCL clock pin. Bit
2
C bus.
Table
Table 16-4
I
2
C
Table 16-4
operation.
16-3. The
2
C inter-
and
• SDNACKI interrupt — This interrupt flag bit indicates
Table 16-4. Master transmit mode GDI/FI status
Table 16-5. STATE field values
Table 16-6. Master receive GDI/FI conditions
The SDA_STAT and SCL_STAT bits indicate the current
state of the SDA and SCL signals. The STATE field indi-
PRELIMINARY SPECIFICATION
GDI
GDI
0
0
1
STATE
0
0
1
the I
transaction. This is an error condition. Once the I
interface has set this interrupt flag, the interface is
idle. The DSPCPU should clear this interrupt flag by
writing a ‘1’ to IIC_CR.CLRSANACKI before re-
attempting this transfer or starting another I
fer.
that an addressed slave receiver device has refused
to acknowledge the current byte of data for an ongo-
ing transfer. This is an error condition. Once the I
interface has set this interrupt flag, the interface is
idle. The DSPCPU should clear this interrupt flag by
writing a ‘1’ to IIC_CR.CLRSDNACKI before retrying
this transfer or starting another.
000
001
010
100
101
011
110
111
2
FI
C bus acknowledges the address to claim the
0
1
X
FI
0
1
X
Meaning
I
RESERVED FOR FUTURE USE
IDLE (MSG is done, awaiting clear GDI to go to
000 state)
Address phase is being processed
BYTE3 (first byte) is being processed
BYTE2 is being processed
BYTE1 is being processed
BYTE0 (last) is being processed
Message is not complete. The IIC_DR is not
empty. No interrupt.
Message is not complete. The IIC_DR is empty
and the requested transmit byte count is not
equal to 0. The DSPCPU must write additional
bytes of the current transfer to the IIC_DR regis-
ter.
Message transmission has completed. The
IIC_DR is empty. The byte transmit count = 0.
2
Message is not complete. IIC_DR is not full.
No interrupt.
IIC_DR contains received data and needs to
be read serviced. More data bytes are
expected since the receive byte count is not
equal to 0.
The transfer has been completed and the
receive byte count is equal to 0. 0 to 4 valid
bytes are in the IIC_DR register awaiting read
servicing by the DSPCPU.
C Interface is idle.
Description
Description
I2C Interface
2
C trans-
16-3
2
2
C
C