PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 266

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 17-9. Test mode select
17.11 TIMING DIAGRAMS
Figure 17-11
data signals and the frame timing.
17.12 POWER DOWN
SSI block can be separately powered down by setting a
bit in the BLOCK_POWER_DOWN register. For a de-
scription of powerdown, see
17-12
Figure 17-12. SSI Serial timing. (FSP = 0, RSD = 0, TSD = 0, TCP = 0, RCP = 0, FMS = 0, FSS = 5, VSS = 4)
Figure 17-11. SSI Serial timing. (FSP = 0, RSD = 0, TSD = 0, TCP = 0, RCP = 0, FMS = 0)
SSI_RXDATA
SSI_TXDATA
SSI_RXCLK
SSI_RXFSX
Bit
0X
10
11
and
Figure 17-12
Normal Operation.
Remote Loopback Test: Direct connection of receiver serial data to transmitter serial data. Transmitter is
clocked with RxCLK. No data loaded to the SSI_RxDR register or RxFIFO buffer and no CPU interrupt is gener-
ated. Useful to allow remote device to test the communication medium and the Rx and Tx front ends.
Local Loopback Test: Feedback is after SSI_TxDR and SSI_RxDR register and serializer/deserializer. Allows
DSPCPU to test the bulk of the Rx and Tx circuits. During Local Loopback Test, an external clock on
SSI_RXCLK should be present to clock the SSI unit.
SSI_RXDATA
SSI_TXDATA
1st DATA
SSI_RXCLK
SSI_RXFSX
1st DATA
PRELIMINARY SPECIFICATION
1st Frame
Chapter 21, “Power Man-
illustrate the timing of the
D0
D0
D15 D14 D13 D12
D15 D14 D13 D12
2nd DATA
2nd DATA
D11 D10 D9
D11 D10 D9
3th DATA
3th DATA
D8
D8
D7
D7
agement.”
plying block powerdown.
If the block enters power-down state while transmission
is enabled, behavior upon power-up is undefined.
D6
D6
Mode
D5
D5
D4
D4
4th DATA
4th DATA
D3
D3
The SSI block should not be active when ap-
D2
D2
D1
D1
D0
D0
D15 D14 D13 D12
D15 D14 D13 D12
Philips Semiconductors
2nd Frame
1st DATA
1st DATA